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1 copyright ? cirrus logic, inc. 2004 (all rights reserved) www.cirrus.com cs8427 96 khz digital audio interface transceiver features z complete eiaj cp1201, iec-60958, aes3, s/pdif compatible transceiver z +5.0 v analog supply (va+) z +3.3 v or +5.0 v digital interface (vl+) z flexible 3-wire serial digital i/o ports z adjustable sample rate up to 96 khz z low jitter clock recovery z pin and microcontroller read/write access to channel status and user data z microcontroller and standalone modes z differential cable driver and receiver z on-chip channel status and user data buffer memories permit block reads & writes z omck system clock mode z decodes audio cd q sub-code general description the cs8427 is a stereo digital audio transceiver with aes3 and serial digital aud io inputs, aes3 and serial digital audio outputs, along with comprehensive control ability through a 4-wi re microcontroller port. channel sta- tus and user data are assembled in block sized buffers, making read/modify/write cycles easy. a low jitter clock recovery mechanism yields a very clean recovered clock from t he incoming aes3 stream. target applications inclu de a/v receivers, cd-r, dvd receivers, multimedia speakers, digital mixing consoles, effects processors, set-top boxes, and computer and au- tomotive audio systems. ordering in formation cs8427-cs 28-pin soic -10 to +70c cs8427-cz 28-pin tssop -10 to +70c CS8427-IS 28-pin soic -40 to +85c cs8427-iz 28-pin tssop -40 to +85c cdb8427 evaluation board i serial audio input clock & data recovery misc. control aes3 s/pdif encoder serial audio output receiver aes3 s/pdif decoder c&ubit data buffer control port & registers output clock generator rxn rxp ilrck isclk sdin olrck osclk sdout txp txn rst omck emph u tcbl sda/ cdout scl/ cclk ad1/ cdin ad0/ cs int va+ agnd filt rerr vl+ dgnd h/s rmck driver jan ?04 ds477f1
cs8427 2 ds477f1 table of contents 1. characteristics and specifications ........................................................................ 5 specified operating conditions . .............. ................ ............. ............. ............. ........... 5 absolute maximum ratings ...... ................ ................ ................ ............. ............. ........... 5 dc electrical characteristics................................................................................... 6 digital input characteristics ..................................................................................... 6 digital interface specifications................................................................................ 6 transmitter characteristics ..................................................................................... 6 switching characteristics .......................................................................................... 7 switching characteristics - serial audio ports................................................. 8 switching characteristics - control port - spi mode...................................... 9 switching characteristics - control port - i2c mode..................................... 10 2. typical connection diagram ...................................................................................... 11 3. general description ..................................................................................................... 12 3.1 audio input/output ports . ................................................................................................ 1 2 3.2 serial control port ....................................................................................................... ..... 12 3.3 channel status and user bi t memory .............................................................................. 12 3.4 aes3 and s/pdif standards documents ........ ................ ............. ............. ............. ......... 13 4. data i/o flow and clocking options ....................................................................... 13 5. three-wire serial audio ports ................................................................................. 15 6. aes3 receiver ............................................................................................................. ....... 16 6.1 omck system clock mode ............................................................................................. 16 6.2 pll, jitter attenuation, and varispeed ............................................................................ 16 6.3 error reporting and hold function .................................................................................. 16 6.4 channel status data handlin g ......................................................................................... 16 6.5 user data handling ........................................................................................................ .. 17 6.6 non-audio auto detection .. ............................................................................................. 17 7. aes3 transmitter ......................................................................................................... .. 18 7.1 transmitted frame and chan nel status boundary timing .............................................. 18 7.2 txn and txp drivers ...................................................................................................... 1 8 8. mono mode operation ................................................................................................... 19 8.1 receiver mono mode ....................................................................................................... 1 9 8.2 transmitter mono mo de ................................................................................................... 19 9. control port description and timing .................................................................... 25 9.1 spi mode .................................................................................................................. ....... 25 9.2 i2c mode .................................................................................................................. ........ 25 9.3 interrupts ................................................................................................................ .......... 25 10. control port register summary ........ ................................................................... 27 10.1 memory address po inter (map) ..................................................................................... 27 11. control port register bit definitions ................................................................ 28 11.1 control 1 (01h) ........................................................................................................... ..... 28 11.2 control 2 (02h) ........................................................................................................... ..... 28 11.3 data flow control (03h)........................ .......................................................................... 2 9 11.4 clock source control (04h) ............................................................................................. 30 11.5 serial audio input port data format (05h)...................................................................... 31 11.6 serial audio outp ut port data format (06h)................................................................... 31 11.7 interrupt 1 status (07h) (read only)............................................................................... 32 11.8 interrupt 2 status (08h) (read only)............................................................................... 33 11.9 interrupt 1 mask (09h).................................................................................................... .33 11.10 interrupt 1 mode msb (0ah ) & interrupt 1 mode lsb (0bh )......................................... 33 11.11 interrupt 2 mask (0 ch) .................................................................................................. 3 4 11.12 interrupt 2 mode msb (0dh) & interr upt 2 mode lsb (0eh) ........................................ 34 11.13 receiver channel status (0fh) (read only) ................................................................ 34
cs8427 ds477f1 3 11.14 receiver error (10h) (read only)........... ...................................................................... 35 11.15 receiver error mask (11h) ........................................................................................... 36 11.16 channel status data buff er control (12h).................................................................... 36 11.17 user data buffer control (13h) ..................................................................................... 37 11.18 q-channel subcode bytes 0 to 9 (14h - 1dh) (read only) ......................................... 37 11.19 omck/rmck ratio (1eh) (read only)........................................................................ 38 11.20 c-bit or u-bit data buffer (20h - 37h) ........................................................................... 38 11.21 cs8427 i.d. and version register (7fh) (read only) ................................................. 38 12. pin description - software mode ........................................................................... 39 13. hardware mode description ................................................................................... 42 13.1 serial audio port formats ....................... ...................................................................... 42 14. pin description - hardware mode .......................................................................... 44 15. applications ............................................................................................................. ...... 46 15.1 reset, power down and start-up .................................................................................. 46 15.2 id code and revision co de .......................................................................................... 46 15.3 power supply, grou nding, and pcb layout ................................................................... 46 15.4 synchronization of multip le cs8427s ............................................................................ 46 16. package dimensions .................................................................................................... 47 17. appendix a: external aes3/spdif/iec 60958 transmitter and receiver compo- nents ......................................................................................................................... ......... 49 17.1 aes3 transmitter external components . ...................................................................... 49 17.2 isolating transformer requirements ............................................................................. 49 17.3 aes3 receiver external components ........................................................................... 50 17.4 isolating transformer requirements ............................................................................. 50 18. appendix b: channel status and user data buffer management ........... 51 18.1 aes3 channel status(c) bit management .................................................................... 51 18.1.1 manually accessing the e buffer ....................................................................... 51 18.1.2 reserving the first 5 bytes in the e buffer ......................................................... 52 18.1.3 serial copy management system (s cms) ....................................................... 52 18.1.4 channel status data e buffer access .............................................................. 52 18.2 aes3 user (u) bit management .................................................................................... 53 18.2.1 mode 1: transm it all zeros ............................................................................... 53 18.2.2 mode 2: block mode ......................... ................................................................ 53 19. appendix c: pll filter .................................................................................................. 5 4 19.1 general .................................................................................................................. ........ 54 19.2 external filter component s ........................................................................................... 55 19.2.1 general ............................................................................................................. 55 19.2.2 capacitor selection . .......................................................................................... 55 19.2.3 circuit board layout ......................................................................................... 55 19.3 component value selectio n .......................................................................................... 56 19.3.1 identifying the part revision ............................................................................. 56 19.3.2 locking to th e rxp/rxn receiver inputs ......................................................... 56 19.3.3 locking to th e ilrck input ............................................................................... 57 19.3.4 jitter tole rance ................................................................................................. 57 19.3.5 jitter attenuation ..... .......................................................................................... 58 20. revision history ......................................................................................................... ... 59 list of figures figure 1. audio port master mode timing .......... ............................................................................ 8 figure 2. audio port slave mode and data inpu t timing................................................................ 8 figure 3. spi mode timing............................. ......................................................................... ......... 9 figure 4. i2c mode timing...................................................................................................... ........ 10 figure 5. recommended connection diagram for software mode .............................................. 11
cs8427 4 ds477f1 figure 6. cs8427 internal block diagram........... .......................................................................... 13 figure 7. software mode audio data flow switch ing options...................................................... 19 figure 8. cs8427 clock routing................................................................................................. .. 20 figure 9. aes3 input to serial audio output, serial audio input to aes3 out ............................. 21 figure 11. input serial port to aes3 transmitter without pll ...... ............. ............. ............. ......... 21 figure 10. aes3 input to serial audio output only ...... ................ ............. ............. ............. ......... 21 figure 12. input serial port to aes3 transmitter with pll ........... ............. ............. ............. ......... 21 figure 13. aes3 receiver timing for u pin output data ............... ............. ............. ............. ......... 22 figure 14. aes3 transmitter timing for c, u and v pin input data ............ ............. ............. ......... 22 figure 15. serial audio input example formats.. .......................................................................... 23 figure 16. serial audio output example formats......................................................................... 24 figure 17. control port timing in spi mode..... ............................................................................. 26 figure 18. control port timing in i2c mode................................................................................... 26 figure 19. hardware mo de....................................................................................................... ..... 42 figure 20. professional output circuit ......................................................................................... .49 figure 21. consumer output cir cuit............................................................................................. .49 figure 22. ttl/cmos output circu it ............................................................................................ 4 9 figure 23. professional input circuit .......................................................................................... ... 50 figure 24. transformerless profe ssional input circuit .................................................................. 50 figure 25. consumer input circuit ................... ........................................................................... .. 50 figure 26. ttl/cmos input circuit.............................................................................................. .50 figure 27. channel status data buffer structure.......................................................................... 51 figure 28. flowchart for readin g the e buffer .............................................................................. 52 figure 29. flowchart for writing the e buffer ................................................................................ 52 figure 30. pll block diagram ... ................................................................................................ ... 54 figure 31. recommended layout example ............ ...................................................................... 55 figure 32. jitter tolerance template ............... ............................................................................ .57 figure 33. revision a .................................... ...................................................................... .......... 58 figure 34. revision a1 .................................. ....................................................................... ......... 58 figure 35. revision a2 using a1 values........................................................................................ 5 8 figure 36. revision a2 using a2* values ............ .......................................................................... 58 list of tables table 1. control register map summary ............ .......................................................................... 27 table 2. hardware mode start-up options.................................................................................... 43 table 3. serial audio output fo rmats available in hardware mode ............................................. 43 table 4. serial audio input formats available in hardware mode................................................ 43 table 5. second line part mark ing .............................................................................................. .56 table 6. locking to rxp/rxn - fs = 8 to 96 khz ......................................................................... 56 table 7. locking to rxp/rxn - fs = 32 to 96 khz ....................................................................... 56 table 8. locking to the ilrck input ............................................................................................ .57 table 9. revision history ...................................................................................................... ........ 59
cs8427 ds477f1 5 1. characteristics and specifications (all min/max characteristics and specifications are guarante ed over the specified operat ing conditions. typical per- formance characteristics and specifications are derived from measurements taken at nominal supply voltages and t a = 25c.) specified operat ing conditions (agnd, dgnd = 0 v, all voltages with respect to 0 v) notes: 1. i2c protocol is supported only in vl+ = 5.0 v mode. absolute maximum ratings (agnd, dgnd = 0 v; all voltages with respect to 0 v. operation beyond these limits may result in permanent damage to th e device. normal operation is not guaranteed at these extremes.) notes: 2. transient currents of up to 100 ma will not cause scr latch-up. parameter symbol min typ max units power supply voltage (note 1) va+ vl+ 4.5 2.85 5.0 3.3 or 5.0 5.5 5.5 v v ambient operating temperature: ?-cs? & ?-cz? ?-is? & ?-iz? t a -10 -40 - - +70 +85 c parameter symbol min max units power supply voltage vl+,va+ - 6.0 v input current, any pin ex cept supplies (note 2) i in -10ma input voltage v in -0.3 (vl+) + 0.3 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c
cs8427 6 ds477f1 dc electrical characteristics (agnd = dgnd = 0 v; all voltages with respect to 0 v.) notes: 3. power down mode is defined as rst = lo with all clocks and data lines held static. 4. normal operation is defined as rst = hi. digital input characteristics digital interface specifications (agnd = dgnd = 0 v; all voltages with respect to 0 v.) notes: 5. at 5.0 v mode, v il = 0.8 v (max), at 3.3 v mode, v il =0.4 v (max). transmitter characteristics parameters symbol min typ max units power-down mode (note 3) supply current in power down va+ vl+ = 3.3 v vl+ = 5.0 v - - - 20 60 60 - - - a a a normal operation (note 4) supply current at 48 khz frame rate va+ vl+ = 3.3 v vl+ = 5.0 v - - - 6.3 30.1 46.5 - - - ma ma ma supply current at 96 khz frame rate va+ vl+ = 3.3 v vl+ = 5.0 v - - - 6.6 44.8 76.6 - - - ma ma ma parameters symbol min typ max units input leakage current i in -110 a differential input voltage, rxp0 to rxn v th -200- mv parameters symbol min max units high-level output voltage (i oh = -3.2 ma), except txp/txn v oh (vl+) - 1.0 - v low-level output voltage (i oh = 3.2 ma), except txp/txn v ol -0.4v high-level output voltage, txp, txn (23 ma at vl+ = 5.0 v) (15.2 ma at vl+ = 3.3 v) (vl+) - 0.7 (vl+) - 0.7 - - v v low-level output voltage, txp, txn (23 ma at vl+ = 5.0 v) (15.2 ma at vl+ = 3.3 v) - - 0.7 0.7 v v high-level input voltage, except rxp, rxn v ih 2.0 (vl+) + 0.3 v low-level input voltage, except rxp, rxn (note 5) v il -0.3 0.4/0.8 v parameters symbol min typ max units txp output resistance vl+ = 5.0 v vl+ = 3.3 v r txp - - 26 40 - - ? ? txn output resistance vl+ = 5.0 v vl+ = 3.3 v r txn - - 26 40 - - ? ?
cs8427 ds477f1 7 switching characteristics (inputs: logic 0 = 0 v, logic 1 = vl+; c l = 20 pf) notes: 6. cycle-to-cycle locking to rxp/rxn using 32 to 96 khz external pll filter components. 7. pll is bypassed (rxd1:0 bits in the clock source co ntrol register set to 10b) , clock is input to the rmck pin. parameter symbol min typ max units rst pin low pulse width 200 - - s omck frequency for omck = 512 * fso 4.1 - 55.3 mhz omck low and high width for omck = 512 * fso 7.2 - - ns omck frequency for omck = 384 * fso 3.1 - 41.5 mhz omck low and high width for omck = 384 * fso 10.8 - - ns omck frequency for omck = 256 * fso 2.0 - 27.7 mhz omck low and high width for omck = 256 * fso 14.4 - - ns pll clock recovery sample rate range 8.0 - 108.0 khz rmck output jitter (note 6) - 200 - ps rms rmck output duty cycle 40 50 60 % rmck input frequency (note 7) 1.8 - 27.7 mhz rmck input low and high width (note 7) 14.4 - - ns aes3 transmitter output jitter - - 1 ns
cs8427 8 ds477f1 switching characteristics - serial audio ports (inputs: logic 0 = 0 v, logic 1 = vl+; c l = 20 pf) notes: 8. the active edges of isclk and osclk are programmable. 9. when osclk, olrck, isclk, and ilrck are derive d from omck they are clocked from its rising edge. when these signals are derived from rmck, they are clocked from its falling edge. 10. the polarity of ilrck and olrck is programmable. 11. no more than 128 sclk per frame. 12. this delay is to prevent the previous i/osclk edge from being interpreted as the first one after i/olrck has changed. 13. this setup time ensures that this i/osclk edge is interpreted as the first one after i/olrck has changed. parameter symbol min typ max units osclk active edge to sdout output valid (note 8) t dpd - - 20 ns sdin setup time befo re isclk active edge (note 8) t ds 20 - - ns sdin hold time after isclk active edge (note 8) t dh 20 - - ns master mode o/rmck to i/osclk active edge delay (note 8, 9) t smd 0 - 10 ns o/rmck to i/olrck delay (note 10) t lmd 0 - 10 ns i/osclk and i/olrck duty cycle - 50 - % slave mode i/osclk period (note 11) t sckw 36 - - ns i/osclk input low width t sckl 14 - - ns i/osclk input high width t sckh 14 - - ns i/osclk active edge to i/olrck edge (note 8, 10, 12) t lrckd 20 - - ns i/olrck edge setup before i/osclk active edge (note 8, 10, 13) t lrcks 20 - - ns sckh sckl sckw t t t t dpd sdout (input) (input) sdin dh t ds t lrcks t lrckd t isclk osclk ilrck olrck t smd t lm d hardware mode software mode isclk osclk (output) ilrck olrck (output) rmck (output) rmck (output) omck (input) figure 1. audio port master mode timing figure 2. audio port slave mode and data input timing
cs8427 ds477f1 9 switching characteristics - control port - spi mode (inputs: logic 0 = 0 v, logic 1 = vl+; c l = 20 pf) notes: 14. if fso or fsi is lower than 46.875 khz, the maximum cclk frequency should be less than 128 fso and less than 128 fsi. this is dictated by the timing requirements necessary to access the channel status and user bit buffer memory. access to the control register file can be carried out at the full 6 mhz rate. the minimum allowable input sample rate is 8 khz, so choosing cclk to be less than or equal to 1.024 mhz should be safe fo r all possible conditions. 15. data must be held for sufficient time to bridge the transition time of cclk. 16. for f sck < 1 mhz. parameter symbol min typ max units cclk clock frequency (note 14) f sck 0-6.0mhz cs high time between transmissions t csh 1.0 - - s cs falling to cclk edge t css 20 - - ns cclk low time t scl 66 - - ns cclk high time t sch 66 - - ns cdin to cclk rising setup time t dsu 40 - - ns cclk rising to data hold time (note 15) t dh 15 - - ns cclk falling to cdout stable t pd - - 50 ns rise time of cdout t r1 - - 25 ns fall time of cdout t f1 - - 25 ns rise time of cclk and cdin (note 16) t r2 - - 100 ns fall time of cclk and cdin (note 16) t f2 - - 100 ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t pd cdout t csh figure 3. spi mode timing
cs8427 10 ds477f1 switching characteristics - control port - i2c mode (note 17 , inputs: logic 0 = 0 v, logic 1 = vl+; c l = 20 pf) notes: 17. i2c protocol is supported only in vl+ = 5.0 v mode. 18. data must be held for sufficient time to bridge the 25 ns transition time of scl. parameter symbol min typ max units scl clock frequency f scl - - 100 khz bus free time between transmissions t buf 4.7 - - s start condition hold time (p rior to first clock pulse) t hdst 4.0 - - s clock low time t low 4.7 - - s clock high time t high 4.0 - - s setup time for repeated start condition t sust 4.7 - - s sda hold time from scl falling (note 18) t hdd 0- - s sda setup time to scl rising t sud 250 - - ns rise time of both sda and scl lines t r - - 25 ns fall time of both sda and scl lines t f - - 25 ns setup time for stop condition t susp 4.7 - - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl figure 4. i2c mode timing
cs8427 ds477f1 11 2. typical connection diagram * a separate analog supply is only necessary in applications where rmck is used for a jitter sensitive task. for applications where rmck is not used for a jitter sensitive task, connect va+ to vd+ via a ferrite bead. keep the decoupling capacitor between va+ and agnd. cs8427 cable termination rxp rxn aes3/ spdif source 3-wire serial audio source ilrck isclk sdin clock source and control rmck omck hardware control rst rerr emph tcbl to other cs8427's cable interface aes3/ spdif equipment txp txn 3-wire serial audio input device olrck osclk sdout microcontroller sda/cdout ad0/cs scl/cclk ad1/cdin u int va+ v l + ferrite * bead +5.0 v analog supply* 0.1 f 0.1 f dgnd filt agnd rfilt cfilt crip h/s +3.3 v or +5.0 v digital supply d a2 / figure 5. recommended conn ection diagram for software mode
cs8427 12 ds477f1 3. general description the cs8427 is an aes3 transceiver intended to be used in digital audio systems. such systems in- clude digital mixing consoles, effects processors, digital recorders and computer multimedia sys- tems. 3.1 audio input/output ports the cs8427 has the following audio ports: ? serial audio input port ? serial audio output port ? aes3 or s/pdif receiver ? aes3 or s/pdif transmitter the serial audio ports use a three-wire format. this consists of a serial audio data stream, a left- right clock defining the boundaries of the audio sample frames, and a serial clock signal clocking the data bits. a serial audio port may operate in either master or slave mode. when a port is a master, it supplies the left-right clock and the serial clock to the exter- nal device that is sending or receiving the serial data . a port in slave mode must have its left-right clock and its serial clock supplied by an external device so that it may send or receive serial audio data. the input sample rate is determined by the stream applied to the serial audio input or to the aes3 re- ceiver. a phase-locked-loop recovers rmck, the input master clock signal , from the chosen input stream. the output from the chip may be through the serial audio output, the aes3 transmitter or from both simultaneously. in some configurations, all audio ports of the chip may be in use at the same time. 3.2 serial control port besides the functional bl ocks already described, the device also has a control port that allows the user to read and write the control registers that configure the part. the control port is capable of operating in either spi or i2c serial mode. this port also has access to buffer memory that allows the user to control what is transmitted in the channel status and user bits of the outgoing aes3 stream. the control port is clocked by the serial clock sig- nal that the user's micro-controller sends it. the mcu can read and write the registers even when the rmck and omck clocks are not running. the channel status and user bit buffer memories de- pend on clocking from rmck and omck. they will not function unless the clocks are running, and the run bit in the clock source control register is set. there is also an interrupt signal associated with the serial control port and the internal registers. the format of the interrupt may be chosen by a reg- ister setting. there are two interrupt status regis- ters and their associated interrupt mask registers. 3.3 channel status and user bit memory the memory architecture consists of three buffers to handle the channel status information, and an- other three buffers to handle the user bits. the data recovery logic extracts the channel status and user bits from the aes3 stream and places them in their respective d buffers. each buffer con- tains 384 bits. this is enough memory to hold a complete block of channel status bits from both a and b channels and a complete block of user bits. when the d buffers are full, the chip transfers their contents into the e buffers. while in the e buffers the channel status and user bits may be read or written through the control port. this allows the user to alter them to suit the needs of the applica- tion. the control bit bsel, in the channel status data buffer control register, determines whether the control port has access to the channel status bits or the user bits. the aes3 encoder reads the channel status and user bits from the f buffers and inserts them into the outgoing aes3 stream. after the f buffers bits are transmitted, the chip transfers the current contents of the e buffers into the f buffers. in applications using aes3 in and aes3 out, the cs8427 can automatically transceive user data that conforms to the iec60958 format. the cs8427 also gives the user access to the bits nec- essary to comply with the serial copy management system (scms). in applications where the user want to read/modi- fy/write the channel status information that re- quires a micro-controller to actively manage the channel status bits. the part also has a feature that allows the first five bytes of channel status
cs8427 ds477f1 13 memory to be configured and transmitted in each channel status block without change. see ?appen- dix a: external aes3/ spdif/iec60958 transmit- ter and receiver components? on page 49 for a tutorial in channel status and user bit manage- ment. 3.4 aes3 and s/pdif standards documents this data sheet assumes that the user is familiar with the aes3 and s/pdif dat a formats. it is advis- able to have current copies of the aes3 and iec60958 specifications on hand for easy refer- ence. the latest aes3 standard is available from the au- dio engineering society or ansi at www.aes.org or www.ansi.org . obtain the latest iec60958 stan- dard from ansi or from the international electro- technical commission at www.iec.ch . the latest eiaj cp-1201 standard is available from the jap- anese electronics bureau. crystal application note an22: overview of digital audio interface data structures contains a useful tutorial on digital audio s pecifications, but it should not be considered a substitute for the standards. the paper, an understanding and implementation of the scms serial copy management system for digital audio transmission , by clifton sanchez, is an excellent tutorial on scms. it is available from the aes as preprint 3518. 4. data i/o flow and clocking options the cs8427 can be configured for several connec- tivity alternatives, called data flows. figure 7. ?soft- ware mode audio data flow switching options? on page 19 shows the data flow switching, along with the control register bits which control the switches; this drawing only shows the audio data paths for simplicity. this drawing only shows the audio data paths for simplicity. figure 8 shows the internal clock routing and the associated control register bits. the clock routing constraints determine which serial audio input aes3 encoder serial audio output receiver rxp rxn ilrck isclk sdin olrck osclk sdout txp txn aes3 txoff aesbp spd1-0 txd1-0 channel status and user data recovery control port control registers channel status bits d user bits d ef e f sda/cdout scl/cclk ad1/cdin ad0/cs int output clock generator omck ad2/emph figure 6. cs8427 internal block diagram
cs8427 14 ds477f1 data routing options are actually usable. users should note that not all the possible data flow switch setting combinations are valid, because of the clock distribution architecture. the aesbp switch, shown in figure 7 , allows a ttl level bi-phase mark encoded data stream con- nected to rxp to be routed to the txp and txn pin drivers. the txoff switch causes the txp and txn outputs to be driven to ground. there are two possible clock sources. the first, designated the recovered clock, is the output of the pll, and is output through the rmck pin. the in- put to the pll can be either the incoming aes3 data stream or the ilrck word rate clock from the serial audio input port. the second clock is input through the omck pin and would normally be a crystal derived stable clock. the clock source control register bits determine which clock is used to operate the cs8427. the cs8427 has another constraint related to the state machine that governs the startup of the part. the startup state machine doesn?t complete its process until the pll has locked unless one is in the transmitter dataflow (see figure 10 ). the con- sequence of this is that the transmitter will not transmit until the pll has locked. if you wish to use the part in transceiver mode and this constraint is a problem, there is a work around. start the part up in its default configuration and allow the pll to lock to a signal on the ilrck pin, then without stopping the part, reconfigure it to the transceiver mode. by studying the following drawings and appropri- ately setting the data flow control and clock source control register bits, the cs8427 can be configured to fit a variety of customer require- ments. please note that a pplications implementing both the serial audio output port and the aes3 transmitter must operate at the same sample rate because they are both controlled by the same clock source. figure 9 shows the entire data path clocked by the pll generated recovered clock. figure 10 illus- trates a standard aes3 receiver function. figure 11 shows a standard aes3 transmitter function without pll. figure 12 shows a standard aes3 transmitter function with pll.
cs8427 ds477f1 15 5. three-wire serial audio ports a 3-wire serial audio input port and a 3-wire serial audio output port is provided. each port can be ad- justed to suit the attached device by setting the control registers. the following parameters are ad- justable: master or slave, serial clock frequency, audio data resolution, left or right justification of the data relative to left/right clock, optional 1-bit cell delay of the 1st data bit, the polarity of the bit clock and the polarity of the left/right clock. by setting the appropriate control bits, many formats are possi- ble. figure 15 shows a selection of common input for- mats, along with the control bit settings. it should be noted that in right justified mode, the serial au- dio output data is ?msb extended?. this means that in a sub-frame where the msb of the data is '1', all bits preceding the msb in the sub-frame will also be '1'. conversely, in a sub-frame where the msb of the data is '0', all bits preceding the msb in the sub-frame will also be '0'. the clocking of the input section of the cs8427 may be derived from the incoming ilrck word rate clock, using the on-chip pll. the pll opera- tion is described in ?aes3 receiver? on page 16 . in the case of use with the serial audio input port, the pll locks onto the leading edges of the ilrck clock. figure 16 shows a selection of common output for- mats, along with the control bit settings. a special aes3 direct output format is included, which allows serial output port access to the v, u, and c bits em- bedded in the serial audio data stream. the p bit is replaced by a bit indicating the location of the z preamble that marks the block start. this format is only available when the se rial audio output port is being clocked by the aes3 receiver recovered clock. in master mode, the left/right clock and the serial bit clock are outputs, derived from the appropriate clock domain master clock. in slave mode, the left/right clock and the serial bit clock are inputs. the left/right clock must be syn- chronous to the appropriate master clock, but the serial bit clock can function in asynchronous burst mode if desired. by appropriate phasing of the left/right clock and control of the serial clocks, cs8427?s can be multiplexed to share one serial port. the left/right clock should be continuous, but the duty cycle does not have to be 50%, provided that enough serial clocks are present in each phase to clock all the data bits. when in slave mode, the serial audio output port must not be set to right justified data. when using the serial audio output port in slave mode with an olrck input which is asynchronous to the port?s data source, an interrupt bit (oslip) is provided to indicate when repeated or dropped samples occur.
cs8427 16 ds477f1 6. aes3 receiver the cs8427 includes an aes3 digital audio re- ceiver and an aes3 digital audio transmitter. a comprehensive buffering scheme provides read/write access to the channel status and user data. this buffering scheme is described in ? ap- pendix b: channel status and user data buffer management ?. the aes3 receiver ac cepts and decodes audio and digital data accord ing to the aes3, iec60958 (s/pdif), and eiaj cp-1201 interface standards. the receiver consists of a differential input stage, accessed through pins rxp and rxn, a pll based clock recovery circuit, and a decoder which separates the audio data from the channel status and user data. external components are used to terminate and isolate the incoming data cables from the cs8427. these components are detailed in ?appendix a: external aes3/spdif/ie c60958 transmitter and receiver components? on page 49 . 6.1 omck system clock mode a special mode is available that allows the clock that is being input through the omck pin to be out- put through the rmck pin. this feature is con- trolled by the swclk bit in control register 1. when the pll loses lock, the frequency of the vco drops to 300 khz. the swclk function al- lows the clock from rmck to be used as a clock in the system without any disruption when input is re- moved from the receiver. this clock switching is done glitch free. none of the internal circuitry that is clocked from the pll is driven by the omck be- ing output from rmck. this function is available only in software mode. 6.2 pll, jitter attenuation, and varispeed please see appendix c for general description of the pll, selection of recommended pll filter com- ponents, and layout considerations. figure 5 shows the recommended configuration of the two capacitors and one resistor that comprise the pll filter. 6.3 error reporting and hold function while decoding the incoming aes3 data stream, the cs8427 can identify several kinds of error, in- dicated in the receiver error register. the un- lock bit indicates whether the pll is locked to the incoming aes3 data. the v bit reflects the cur- rent validity bit status. the bip (bi-phase) error bit indicates an error in incoming bi-phase coding. the par (parity) bit indicates a received parity er- ror. the error bits are ?sticky?: they are set on the first occurrence of the associated error and will remain set until the user reads the register through the control port. this enables the register to log all un- masked errors that occurred since the last time the register was read. the receiver error mask register allows masking of individual errors. the bits in this register serve as masks for the corresponding bits of the receiv- er error register. if a mask bit is set to 1, the error is unmasked, which implies the following: its occur- rence will be reported in the receiver error register, induce a pulse on rerr, invoke the occurrence of a rerr interrupt, and affect the current audio sample according to the status of the hold bits. the hold bits allow a choi ce of holding the previ- ous sample, replacing the current sample with zero (mute), or not changing the current audio sample. if a mask bit is set to 0, the error is masked, which implies the following: its occurrence will not be re- ported in the receiver error register, will not induce a pulse on rerr or generate a rerr interrupt, and will not affect the current audio sample. the qcrc and ccrc errors do not affect the current audio sample, even if unmasked 6.4 channel status data handling the first two bytes of the channel status block are decoded into the receiver channel status regis- ter. the setting of the chs bit in the channel sta- tus data buffer control register determines whether the channel status decodes are from the a channel (chs = 0) or b channel (chs = 1). the pro (professional) bit is extracted directly. for consumer data, the copy (copyright) bit is ex- tracted, and the category code and l bits are de- coded to determine scms status, indicated by the orig (original) bit. if the category code is set to
cs8427 ds477f1 17 general on the incoming aes3 stream, copyright will always be indicated even when the stream in- dicates no copyright. finally, the audio bit is ex- tracted and used to set an audio indicator, as described in the non-audio auto-detection section below. if 50/15 s pre-emphasis is detected, the state of the emph pin is adjusted accordingly. the encoded channel status bits which indicate sample word length are decoded according to aes3-1992 or iec 60958. audio data routed to the serial audio output port is unaffected by the word length settings; all 24 bits are passed on as re- ceived. ?appendix b: channel status and user data buffer management? on page 51 describes the overall handling of channel status and user bit data. 6.5 user data handling the incoming user data is buffered in a user acces- sible buffer. various automatic modes of re-trans- mitting received user data are provided. the appendix: channel status and user data buffer management describes the overall handling of cs and u data. received user data may also be output to the u pin, under the control of a control register bit. de- pending on the data flow and clocking options se- lected, there may not be a clock available to qualify the u data output. figure 13 illustrates the timing. if the incoming user data bits have been encoded as q-channel subcode, the data is decoded and presented in ten consecutive register locations. an interrupt may be enabled to indicate the decoding of a new q-channel block, which may be read through the control port. 6.6 non-audio auto detection an aes3 data stream may be used to convey non- audio data, thus it is important to know whether the incoming aes3 data stream is digital audio or not. this information is typica lly conveyed in channel status bit 1 (audio ), which is extracted automati- cally by the cs8427. however, certain non-audio sources, such as ac3 or mpeg encoders, may not adhere to this convention, and the bit may not be properly set. the cs8427 aes3 receiver can de- tect such non-audio data. this is accomplished by looking for a 96-bit sync code, consisting of 0x0000, 0x0000, 0x0000, 0x0000, 0xf872, and 0x4e1f. when the sync code is detected, an inter- nal autodetect signal will be asserted. if no ad- ditional sync codes are detected within the next 4096 frames, autodetect will be de-asserted until another sync code is detected. the audio bit in the receiver channel status register is the logi- cal or of autodetect and the received chan- nel status bit 1. if non-audio data is detected, the data is still processed exactly as if it were normal audio. it is up to the user to mute the outputs as re- quired.
cs8427 18 ds477f1 7. aes3 transmitter the aes3 transmitter encodes and transmits au- dio and digital data according to the aes3, iec60958 (s/pdif), and eiaj cp-1201 interface standards. audio and control data are multiplexed together and bi-phase mark encoded. the result- ing bit stream is driven to an output connector ei- ther directly or through a transformer. the transmitter clock may be derived from the clock input pin omck, or from the incoming data. if omck is asynchronous to the data source, an in- terrupt bit (tslip) is provided that will go high ev- ery time a data sample is dropped or repeated. be aware that the pattern of slips does not have hys- teresis and so the occurrence of the interrupt con- dition is not deterministic. the channel status (c) and user channel (u) bits in the transmitted data stream are taken from storage areas within the cs8427. the user can manually access the internal storage or configure the cs8427 to run in one of several automatic modes. the appendix: channel status and user data buffer management provides detailed descriptions of each automatic mode and describes methods of manually accessing the storage areas. the trans- mitted user data can optionally be input through the u pin, under the control of a control port regis- ter bit. figure 13 shows the timing requirements for clocking u data through the u pin. 7.1 transmitted frame and channel status boundary timing the tcbl pin is used to control or indicate the start of transmitted channel status block boundaries and may be used as an input or output. in some applications, it may be necessary to con- trol the precise timing of the transmitted aes3 frame boundaries. this may be achieved in three ways: a) with tcbl set to input, driving tcbl high for >3 omck clocks will cause a frame start, as well as a new channel status block start. b) if the aes3 output comes from the aes3 input, setting tcbl as output will cause aes3 output frame boundaries to align with aes3 input frame boundaries. c) if the aes3 output comes from the serial audio input port while the port is in slave mode and tcbl is set to output, the start of the a channel sub- frame will be aligned with the leading edge of il-ck. 7.2 txn and txp drivers the line drivers are low skew, low impedance, dif- ferential outputs capable of driving cables directly. both drivers are set to ground during reset (rst = low), when no aes3 transmit clock is pro- vided, and optionally under the control of a register bit. the cs8427 also allows immediate mute of the aes3 transmitter audio dat a through a control reg- ister bit. external components are used to terminate and isolate the external cable from the cs8427. these components are detailed in appendix a: external aes3/spdif/iec60958 trans mitter and receiver components .
cs8427 ds477f1 19 8. mono mode operation an aes3 stream may be used in more than one way to transmit 96 khz sample rate data. one method is to double the frame rate of the current format. this results in a stereo signal with a sample rate of 96 khz, carried over a single twisted pair cable. an alternate method is implemented using the two sub-frames in a 48 khz frame rate aes3 signal to carry consecutive samples of a mono sig- nal, resulting in a 96 khz sample rate stream. this allows older equipment, whose aes3 transmitters and receivers are not rated for 96 khz frame rate operation, to handle 96 khz sample rate informa- tion. in this ?mono m ode?, two aes3 cables are needed for stereo data transfer. the cs8427 of- fers mono mode operation for the aes3 receiver and the aes3 transmitter. the receiver and trans- mitter sections may be independently set to mono mode through the mmr and mmt control bits. 8.1 receiver mono mode the receiver mono mode effectively doubles the input frame rate, fsi. the clock output on the rmck pin tracks fsi, and thus is doubled in fre- quency compared to stereo mode. the receiver will run at a frame rate of fsi/2, and the serial audio output port will run at fsi. sub-frame a data will be routed to both the left and right data fields on sd-out. similarly, sub-frame b data will be routed to both the left and right data fields of the next word clock cycle of sdout. using receiver mono mode is only necessary if the serial audio output port must run at 96 khz. if the cs8427 is kept in normal stereo mode and re- ceives aes3 data arranged in mono mode, the se- rial audio output port will run at 48 khz, with left and right data fields repr esenting consecutive au- dio samples. 8.2 transmitter mono mode in transmitter mono mode, the input port will run at the audio sample rate (fso), while the aes3 trans- mitter frame rate will be at fso/2. consecutive left or right channel serial audio data samples may be selected for transmission on the a and b sub- frames, and the channel status block transmitted is also selectable. using transmitter mono m ode is only necessary if the incoming audio sample rate is already at 96 khz and contains both left and right audio data words. the ?mono mode? aes3 output stream may also be achieved by keeping the cs8427 in normal stereo mode and placing consecutive audio sam- ples in the left and right positions of an incoming data stream with a 48 khz word rate. serial audio input aes3 encoder serial audio output receiver rxp rxn ilrck isclk sdin olrck osclk sdout txp txn aes3 txoff aesbp spd txd mux mux figure 7. software mode audio data flow switching options
cs8427 20 ds477f1 sims pll txp txn sdout osclk olrck omck rmck rxp ilrck isclk sdin mux mux mux swclk unlock 0 1 0 1 0 1 channel status memory user bit memory transmit aes3 serial audio output inc rxd0 mux 0 1 outc serial audio input rxd1 mux 0 1 clk[1:0] rmckf figure 8. cs8427 clock routing note: when swclk mode is enabled, signal input on omck is only output through rmck and not routed back through the rxd1 multiplexer; rmck is not bi-directional in this mode. *
cs8427 ds477f1 21 aes3 encoder &driver serial audio output olrck osclk sdout txp txn pll rmck txd1-0: spd1-0: outc: inc: rxd1-0: 01 10 1 0 01 clock source control bits data flow control bits aes3 rx & decode rxp rxn serial audio input ilrck isclk sdin figure 9. aes3 input to serial audio output, serial audio input to aes3 out note: applications impl ementing both the seri- al audio output port and the aes3 transmitter must operate at the same sample rate because they are both controlled by the same clock source. omck txd1-0: spd1-0: outc: inc: rxd1-0: 01 01 0 1 00 clock source control bits data flow control bits aes3 rx & decode i lrck isclk sdin txp txn serial au d io in p ut figure 11. input serial port to aes3 transmitter without pll serial audio output olrck osclk sdout pll rmck txd1-0: spd1-0: outc: inc: rxd1-0: 10 10 1 0 01 clock source control bits data flow control bits aes3 rx & decode rxp rxn txoff : 1 figure 10. aes3 input to serial audio output only rmck txd1-0: spd1-0: outc: inc: rxd1-0: 01 01 1 0 00 clock source control bits data flow control bits aes3 rx & decode ilrck isclk sdin txp txn serial au d io in p ut pll figure 12. input serial port to aes3 transmitter with pll note: in this mode, ilrck and isclk are inputs only.
cs8427 22 ds477f1 vlrck u output vlrck is a virtual word clock, which may not exist, but is used to illustrate the u timing. vlrck duty cycle is 50%. vlrck frequency is always equal to the incoming frame rate. if the serial audio output port is in master mode, vlrck = olrck. if the serial audio output port is in slave mode, then vlrck needs to be externally created, if required. u transitions are aligned within 1% of vlrck period to vlrck edges figure 13. aes3 receiver timing for u pin output data vcu[0] vcu[1] vcu[2] vcu[3] vcu[4] vlrck data [4] data [5] data [6] data [7] data [8] data [0] data [1] data [2] data [3] data [4] txp(n) z y x y x aes3 transmitter in stereo mode u[0] u[2] tcbl in or out vlrck u input data [4] data [5] data [6] data [7] data [8] sdin input data [0]* data [2]* data [4]* txp(n) output z y x * assume mmtlr = 0 tsetup => 7.5% aes3 frame time thold = 0 tsetup thold data [1]* data [3]* data [5]* txp(n) output zy x aes3 transmitter in mono mode * assume mmtlr = 1 tsetup => 15% aes3 frame time thold = 0 vlrck is a virtual word clock, which may not exist, is used to illustrate the cuv timing. vlrck duty cycle is 50%. in stereo mode, vlrck frequency = aes3 frame rate . in mono mode, alrck frequency = 2xaes3 frame rate. if the serial audio input port is on slave mode and tc bl is an output, then vlrck=ilrck if silrpol=0 and vlrck= ilrck if silrpol =1. if the serial audio input port is in master mode and tcbl is an input, then vlrck=ilrck if silrpol=0 and vlrck= ilrck if silrpol =1. tth tth > 3omck if tcbl is input tth > 3omck if tcbl is input tth figure 14. aes3 transmitter timing for c, u and v pin input data
cs8427 ds477f1 23 ilrck isclk sdin 2 left justified (in) msb lsb left right msb i s (in) right justified (in) msb lsb msb lsb msb left right msb lsb msb lsb left right lsb msb lsb ilrck isclk sdin ilrck isclk sdin figure 15. serial audio input example formats x = don?t care to match format, but does need to be set to the desired setting + i2s can accept an arbitrary number of bits , determined by the number of isclk cycles * see serial input port data format register bit descriptions for an explanation of the meaning of each bit sims* sisf* sires*[1:0] sijust* sidel* sispol* silrpol* left justified x x 00+ 0 0 0 0 i2s x x 00+ 0 1 0 1 right justified x x xx 1 0 0 0
cs8427 24 ds477f1 msb lsb left right msb i s (out) olrck osclk sdout olrck osclk sdout 2 left justified (out) msb lsb olrck osclk sdout msb lsb msb left right aes3 direct (out) vz uc lsb lsb vz uc right justified (out) olrck osclk sdout msb lsb msb lsb msb left right msb lsb left right lsb msb lsb msb extended msb extended msb ex figure 16. serial audio output example formats x = don?t care to match format, but does need to be set to the desired setting * see serial output data format register bit descriptions for an explanation of the meaning of each bit soms* sosf* sores[1:0]* soj ust* sodel* sospol* solrpol* left justified x x xx 0 0 0 0 i2s x x xx 0 1 0 1 right justified 1 x xx 1 0 0 0 aes3 direct x x 11 0 0 0 0
cs8427 ds477f1 25 9. control port description and timing the control port is used to access the registers, al- lowing the cs8427 to be configured for the desired operational modes and formats. in addition, chan- nel status and user data may be read and written through the control port. the operation of the con- trol port may be completely asynchronous with re- spect to the audio sample rates. however, to avoid potential interference problems, the control port pins should remain static if no operation is re- quired. the control port has two modes: spi and i2c, with the cs8427 acting as a slave device. spi mode is selected if there is a high to low transition on the ad0/cs pin after the rst pin has been brought high. i2c mode is selected by connecting the ad0/cs pin to vl+ or dgnd, thereby permanently selecting the desired ad0 bit address state. 9.1 spi mode in spi mode, cs is the cs8427 chip select signal; cclk is the control port bit clock (input into the cs8427 from the microcontroller); cdin is the in- put data line from the microcontroller; cdout is the output data line to the microcontroller. data is clocked in on the rising edge of cclk and out on the falling edge. figure 17 shows the operation of the control port in spi mode. to write to a register, bring cs low. the first seven bits on cdin form the chip address and must be 0010000. the eighth bit is a read/write in- dicator (r/w ), which should be low to write. the next eight bits form the memory address pointer (map), which is set to the address of the register that is to be updated. the next eight bits are the data which will be placed into the register designat- ed by the map. during writes, the cdout output stays in the hi-z state. it may be externally pulled high or low with a 47 k ? resistor, if desired. there is a map auto increment capability, enabled by the incr bit in the map register. if incr is a ze- ro, the map will stay constant for successive read or writes. if incr is set to a 1, then the map will au- toincrement after each byte is read or written, al- lowing block reads or writes of successive registers. to read a register, the map has to be set to the correct address by execut ing a partial write cycle which finishes (cs high) immediately after the map byte. the map auto increment bit (incr) may be set or not, as desired. to begin a read, bring cs low, send out the chip address, and set the read/write bit (r/w ) high. the next falling edge of cclk will clock out the msb of the addressed register (cdout will leave the high impedance state). if the map auto increment bit is set to 1, the data for successive registers will appear consecu- tively. 9.2 i2c mode in i2c mode, sda is a bidirectional data line. data is clocked into and out of the part by scl, with the clock to data relationship as shown in figure 18 . there is no cs pin. each individual cs8427 is giv- en a unique address. pins ad0 and ad1 form the two least significant bits of the chip address and should be connected to vl+ or dgnd as desired. the emph pin is used to set the ad2 bit, by con- necting a resistor from the emph pin to vl+ or to dgnd. the state of the pin is sensed while the cs8427 is being reset. the upper four bits of the seven bit address field are fixed at 0010. to com- municate with a cs8427, the chip address field, which is the first byte sent to the cs8427, should be 0010 followed by the settings of the emph , ad1, and ad0. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address pointer (map) which selects the register to be read or written. if the operation is a read, the contents of the register pointed to by the map will be output. setting the auto increment bit in map allows successive reads or writes of consecutive registers. each byte is separated by an acknowledge bit, ack, which is output from the cs8427 after each input byte is read. the ack bit is input to the cs8427 from the microcontroller af- ter each transmitted byte. i2c mode is supported only with vl+ = 5.0 v. 9.3 interrupts the cs8427 has a comprehensive interrupt capa- bility. the int output pin is intended to drive the in- terrupt input pin on the host microcontroller. the int pin may be set to be active low, active high, or active low with no active pull-up transistor. this last
cs8427 26 ds477f1 mode is used for active low, wired-or hook-ups with multiple peripherals connected to the micro- controller interrupt input pin. many conditions can caus e an interrupt, as listed in the interrupt status register descriptions. each source may be masked off using mask register bits. in addition, each source may be set to rising edge, falling edge, or level sensitive. combined with the option of level sensitive or edge sensitive modes within the microcontroller, many different set-ups are possible depending on the needs of the equipment designer. map msb lsb data byte 1 byte n r/w r/w address chip address chip cdin cclk cs cdout msb lsb msb lsb 0010000 0010000 map = memor y address pointer, 8 bits, msb first high impedance figure 17. control port timing in spi mode sda scl 0010 ad2-0 r/w start ack data7-0 ack data7-0 ack stop note 2 note 1 note 1: ad2 is derived from a resistor attached to the emph pin, note 2: if operation is a write, this byte contains the memory address pointer, map ad1 and ad0 are determined by the state of the corresponding pins note 3: if operation is a read, the last bit of the read should be a nack(high) note 3 figure 18. control port timing in i2c mode
cs8427 ds477f1 27 10. control port register summary 10.1 memory address pointer (map) incr - auto increment address control bit default = ?0? 0 - disable 1 - enable map6:map0 - register address note: reserved registers must not be written to during norm al operation. some reserved registers are used for test modes, which can completely alter the normal operation of the cs8427. addr (hex) function 7 6 5 4 3 2 1 0 00 reserved 00 0 0 0 0 0 0 01 control 1 swclk vset mutesao muteaes 0 int1 int0 tcbld 02 control 2 0 hold1 hold0 rmckf mmr mmt mmtcs mmtlr 03 data flow control 0 txoff aesbp txd1 txd0 spd1 spd0 0 04 clock source control 0 run clk1 clk0 outc inc rxd1 rxd0 05 serial input format sims sisf sires1 sires0 sijust sidel sispol silrpol 06 serial output format soms sosf sores1 sores0 sojust sodel sospol solrpol 07 interrupt 1 status tslip oslip 0 0 0 detc eftc rerr 08 interrupt 2 status 00 0 0detueftuqch0 09 interrupt 1 mask tslipm oslipm 0 0 0 detcm eftcm rerrm 0a interrupt 1 mode (msb) tslip1 oslip1 0 0 0 detc1 eftc1 rerr1 0b interrupt 1 mode (lsb) tslip0 oslip0 0 0 0 detc0 eftc0 rerr0 0c interrupt 2 mask 0 0 0 0 detum eftum qchm 0 0d interrupt 2 mode (msb) 0 0 0 0 detu1 eftu1 qch1 0 0e interrupt 2 mode (lsb) 0 0 0 0 detu0 eftu0 qch0 0 0f receiver cs data aux3 aux2 aux1 aux0 pro audio copy orig 10 receiver errors 0 qcrc ccrc unlock v conf bip par 11 receiver error mask 0 qcrcm ccrcm unlockm vm confm bipm parm 12 cs data buffer control 0 0 bsel cbmr detci eftci cam chs 13 u data buffer control 0 0 0 ud ubm1 ubm0 detui eftui 14-1d q sub-code data 1e omck/rmck ratio orr7 orr6 orr5 orr4 orr3 orr2 orr1 orr0 1f reserved 20-37 c or u data buffer 7f id and version id3 id2 id1 id0 ver3 ver2 ver1 ver0 table 1. control register map summary 7 6 543210 incr map6 map5 map4 map3 map2 map1 map0
cs8427 28 ds477f1 11. control port register bit definitions 11.1 control 1 (01h) swclk - controls output of omck on rmck when pll loses lock default = ?0? 0 - rmck default function 1 - omck output on rmck pin vset - transmitted validity bit level default = ?0? 0 - indicates data is va lid, linear pcm audio data 1 - indicates data is invalid or not linear pcm audio data mutesao - mute control for the serial audio output port default = ?0? 0 - not muted 1 - muted muteaes - mute control for th e aes transmitter output default = ?0? 0 - not muted 1 - muted int1:int0 - interrupt output pin (int) control default = ?00? 00 - active high; high output indicates interrupt condition has occurred 01 - active low, low output indicate s an interrupt condition has occurred 10 - open drain, active low. requires an external pull up resistor on the int pin. 11 - reserved tcbld - transmit channel status bloc k pin (tcbl) direction specifier default = ?0? 0 - tcbl is an input 1 - tcbl is an output 11.2 control 2 (02h) hold1:hold0 - determine how received audio sample is affected when a receiver error occurs default = ?00? 00 - hold the last valid audio sample 01 - replace the current audio sample with 00 (mute) 10 - do not change the received audio sample 11 - reserved rmckf - select recovered master clock output pin frequency. default = ?0? 0 - rmck is equal to 256 * fsi 1 - rmck is equal to 128 * fsi 7 6 543210 swclk vset mutesao muteaes 0 int1 int0 tcbld 7 6 543210 0 hold1 hold0 rmckf mmr mmt mmtcs mmtlr
cs8427 ds477f1 29 mmr - select aes3 receiver mono or stereo operation default = ?0? 0 - normal stereo operation 1 - a and b subframes treated as consecutive sample s of one channel of data. data is duplicated to both left and right parallel outputs of the aes rece iver block. the input samp le rate (fsi) is doubled compared to mmr=0 mmt - select aes3 transmitter mono or stereo operation default = ?0? 0 - normal stereo operation 1 - output either left or right channel in puts into consecutive su bframe outputs (mono mode, left or right is determined by mmtlr bit) mmtcs - select a or b channel status data to transmit in mono mode default = ?0? 0 - use channel a cs data for the a subframe and use channel b cs data for the b subframe 1 - use the same cs data for both the a and b subframe outputs. if mmtlr = 0, use the left channel cs data. if mmtlr = 1, use the right channel cs data. mmtlr - channel select ion for aes transmitter mono mode default = ?0? 0 - use left channel input data for consecutive subframe outputs 1- use right channel input data for consecutive su bframe outputs 11.3 data flow control (03h) the data flow control register configur es the flow of audio data to/from the following blocks: serial audio input port, serial audio output port, aes3 receiver, and aes3 transmit ter. in conjunction with the clock source control regis- ter, multiple receiver/trans mitter/transceiver modes may be selected. the output data should be muted prior to changing bits in this register to avoid transients. txoff - aes3 transmitter out put driver control default = ?0 0 - aes3 transmitter output pi n drivers normal operation 1 - aes3 transmitter output pin drivers drive to 0 v. aesbp - aes3 bypass mode selection default = ?0? 0 - normal operation 1 - connect the aes3 transm itter driver input direct ly to the rxp pin, wh ich becomes a normal ttl threshold digital input. the transmitter clock (selecting using the outc bit in th e clock source control) must be present for the bypass mode to work. txd1:txd0 - aes3 transmitter data source default = ?01? 00 - reserved 01 - serial audio input port 10 - aes3 receiver 11 - reserved 7 6 543210 0 txoff aesbp txd1 txd0 spd1 spd0 0
cs8427 30 ds477f1 spd1:spd0 - serial audio output port data source default = ?10? 00 - reserved 01 - serial audio input port 10 - aes3 receiver 11 - reserved 11.4 clock source control (04h) this register configures the clock sources of various bloc ks. in conjunction with the data flow control register, var- ious receiver/transmitter/transceiver modes may be selected. run - controls the internal clocks, allowing the cs8427 to be placed in a ?powered down?, low current consumption, state. default = ?0? 0 - internal clocks are stopped. internal state machines are reset. the fully static control port is operational, allowing registers to be read or changed. reading and writing the u and c data buffers is not possible. powe r consumption is low. 1 - normal part operation. this bit must be written to the 1 state to allow the cs8427 to begin operation. all input clocks should be stable in frequency and phase when run is set to 1. clk1:0 - output side master clock input (omck) frequency to output sample rate (fso) ra tio selector. if these bits are changed during normal operation, then always stop the cs8427 first (run = 0), write the new value, then start the cs8427 (run = 1). default = ?00? 00 - omck frequency is 256 * fso 01 - omck frequency is 384 * fso 10 - omck frequency is 512 * fso 11 - reserved outc - output time base default = ?0? 0 - omck input pin, modified by the selected divide ratio bits clk1:0. 1 - recovered input clock inc - input time base clock source default = ?0? 0 - recovered input clock 1 - omck input pin, modified by the selected divide ratio bits clk1:0. rxd1:0 - recovered input clock source default = ?00? 00 - 256 * fsi, where fsi is derived from the ilrck pin (only possible when the serial audio in put port is in slave mode) 01 - 256 * fsi, where fsi is deri ved from the aes3 input frame rate 10 - bypass the pll and apply an external 256 * fsi clock through the rmck pin. the aes3 receiver is held in synchronous reset. this setting is useful to prevent unlock interrupts when using an external rmck and inputting data through the serial audio input port. 11 - reserved. 7 6 543210 0 run clk1 clk0 outc inc rxd1 rxd0
cs8427 ds477f1 31 11.5 serial audio input port data format (05h) sims - master/slave mode selector default = ?0? 0 - serial audio input port is in slave mode 1 - serial audio input port is in master mode sisf - isclk frequency (for master mode) default = ?0? 0 - 64 * fsi 1 - 128 * fsi sires1:0 - resolution of the input data, for right-justified formats default = ?00? 00 - 24 bit resolution 01 - 20 bit resolution 10 - 16 bit resolution 11 - reserved sijust - justification of sdin data relative to ilrck default = ?0? 0 - left-justified 1 - right-justified sidel - delay of sdin data relative to ilrck, for left-justif ied data formats default = ?0? 0 - msb of sdin data occurs in the fi rst isclk period a fter the ilrck edge 1 - msb of sdin data occurs in the second isclk period after the ilrck edge sispol - isclk clock polarity default = ?0? 0 - sdin sampled on rising edges of isclk 1 - sdin sampled on falling edges of isclk silrpol - ilrck clock polarity default = ?0? 0 - sdin data is fo r the left channel when ilrck is high 1 - sdin data is for the right channel when ilrck is high 11.6 serial audio output port data format (06h) soms - master/slave mode selector default = ?0? 0 - serial audio output port is in slave mode 1 - serial audio output port is in master mode sosf - osclk frequency (for master mode) default = ?0? 0 - 64 * fso 1 - 128 * fso 7 6 543210 sims sisf sires1 sires0 sijust sidel sispol silrpol 7 6 543210 soms sosf sores1 sores0 sojust sodel sospol solrpol
cs8427 32 ds477f1 sores1:0 - resolution of the output data on sdout and on the aes3 output default = ?00? 00 - 24-bit resolution 01 - 20-bit resolution 10 - 16-bit resolution 11 - direct copy of the receiv ed nrz data from the aes3 receiver (including c, u, and v bits, the time slot normally occupi ed by the p bit is used to indicate the location of the block start, sdout pin only, serial audio output port clock must be derived from the aes3 receiver recovered clock) sojust - justification of sdou t data relative to olrck default = ?0? 0 - left-justified 1 - right-justified (master mode only) sodel - delay of sdout data relative to olrck, for left-justified data formats default = ?0? 0 - msb of sdout data occurs in the fi rst osclk period after the olrck edge 1 - msb of sdout data occurs in the second osclk period after the olrck edge sospol - osclk clock polarity default = ?0? 0 - sdout transitions occur on falling edges of osclk 1 - sdout transitions occur on rising edges of osclk solrpol - olrck clock polarity default = ?0? 0 - sdout data is for the left channel when olrck is high 1 - sdout data is for the right channel when olrck is high 11.7 interrupt 1 status (07h) (read only) for all bits in this register, a ?1? means the associated interrupt condition has o ccurred at least once since the register was last read. a ?0? means the associated interrupt conditi on has not occurred since the last reading of the register. reading the register resets all bits to 0, unless the interrupt mode is set to le vel and the interrupt source is still true. status bits that are masked off in the a ssociated mask register will always be ?0? in this register. this register defaults to 00h. tslip - aes3 transmitter source data slip interrupt. in data flows where omck, which cloc ks the aes3 transm itter, is asynchronous to the data source, this bit will go high every time a data sa mple is dropped or repe ated. when tcbl is an input, this bit will go high on receipt of a new tcbl signal. oslip - serial audio output port data slip interrupt. when the serial audio output port is in slave mode , and olrck is asynchronous to the port data source, this bit will go high every time a dat a sample is dro pped or repeated. detc - d to e c-buffer transfer interrupt. the source for this bit is true during the d to e buff er transfer in the c bit buffer management process. eftc - e to f c-buffer transfer interrupt. the source for this bit is true during the e to f buffer transfer in the c bit buffer management process. rerr - a receiver error has occurred. the receiver error register may be read to determine the nature of the error which caused the interrupt. 7 6 543210 tslip oslip 0 0 0 detc eftc rerr
cs8427 ds477f1 33 11.8 interrupt 2 status (08h) (read only) for all bits in this register, a ?1? means the associated interrupt condition has o ccurred at least once since the register was last read. a ?0? means the associated interrupt conditi on has not occurred since the last reading of the register. reading the register resets all bits to 0, unless the interrupt mode is set to le vel and the interrupt source is still true. status bits that are masked off in the a ssociated mask register will always be ?0? in this register. this register defaults to 00h. detu - d to e u-buffer transfer in terrupt. (block mode only) the source of this bit is true during the d to e buffer transfer in the u bit buffer management process. eftu - e to f u-buffer transfer in terrupt. (block mode only) the source of this bit is true during the e to f bu ffer transfer in the u bit buffer management process. qch - a new block of q-subcode data is available for reading. the data must be co mpletely read within 588 aes3 frames after the interrupt occurs to avoid corruption of the data by the next block. 11.9 interrupt 1 mask (09h) the bits of this register serve as a mask for the interrupt 1 register. if a mask bit is set to 1, the error is unmasked, meaning that its occurrence will af fect the int pin and t he status register. if a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the int pin or the status regi ster. the bit positions align with the corre- sponding bits in the interrupt 1 regi ster. this register defaults to 00h. 11.10 interrupt 1 mode msb (0ah) & interrupt 1 mode lsb (0bh) the two interrupt mode registers form a 2-bit code for each interrupt register 1 function. there are three ways to set the int pin active in accordance with the interrupt co ndition. in the rising edge ac tive mode, the int pin be- comes active on the arrival of the interrupt condition. in the falling edge active mode, the int pin becomes active on the removal of the interrupt condition. in level active mode, the int interrupt pin becomes active during the in- terrupt condition. be awar e that the active level (active high or low) only depends on the in t[1:0] bits. these reg- isters default to 00. 00 - rising edge active 01 - falling edge active 10 - level active 11 - reserved 7 6 543210 0000detueftuqch0 7 6 543210 tslipm oslipm 0 0 0 detcm eftcm rerrm 7 6 543210 tslip1 oslip1 0 0 0 detc1 eftc1 rerr1 tslip0 oslip0 0 0 0 detc0 eftc0 rerr0
cs8427 34 ds477f1 11.11 interrupt 2 mask (0ch) the bits of this register serve as a mask for the interrupt 2 register. if a mask bit is set to 1, the error is unmasked, meaning that its occurrence will af fect the int pin and t he status register. if a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the int pin or the status regi ster. the bit positions align with the corre- sponding bits in the interrupt 2 regi ster. this register defaults to 00h. 11.12 interrupt 2 mode msb (0dh) & interrupt 2 mode lsb (0eh) the two interrupt mode registers form a 2-bit code for each interrupt register 1 function. there are three ways to set the int pin active in accordance with the interrupt co ndition. in the rising edge ac tive mode, the int pin be- comes active on the arrival of the interrupt condition. in the falling edge active mode, the int pin becomes active on the removal of the interrupt condition. in level active mode, the int interrupt pin becomes active during the in- terrupt condition. be awar e that the active level (active high or low) only depends on the in t[1:0] bits. these reg- isters default to 00. 00 - rising edge active 01 - falling edge active 10 - level active 11 - reserved 11.13 receiver channel status (0fh) (read only) the bits in this register can be associated with either channel a or b of the received data. the desired channel is selected with the chs bit of the channe l status data buffer control register. aux3:0 - incoming auxiliary data field width, as indicated by the incoming channel stat us bits, decoded according to iec60958 and aes3. 0000 - auxiliary da ta is not present 0001 - auxiliary data is 1 bit long 0010 - auxiliary da ta is 2 bits long 0011 - auxiliary da ta is 3 bits long 0100 - auxiliary data is 4 bits long 0101 - auxiliary da ta is 5 bits long 0110 - auxiliary da ta is 6 bits long 0111 - auxiliary da ta is 7 bits long 1000 - auxiliary da ta is 8 bits long 1001 - 1111 reserved pro - channel status block format indicator 0 - received channel status block is in consumer format 1 - received channel status block is in professional format 7 6 543210 0 0 0 0 detum eftum qchm 0 7 6 543210 0 0 0 0 detu1 eftu1 qch1 0 0 0 0 0 detu0 eftu0 qch0 0 7 6 543210 aux3 aux2 aux1 aux0 pro audio copy orig
cs8427 ds477f1 35 audio - audio indicator 0 - received data is linearly coded pcm audio 1 - received data is no t linearly coded pcm audio copy - scms copyright indicator 0 - copyright asserted 1 - copyright not asserted if the category code is set to genera l in the incoming aes3 stream, copyrigh t will always be indicated by copy, even when the stream indicates no copyright. orig - scms generation indicator, decoded from the category code and the l bit. 0 - received data is 1st generation or higher 1 - received data is original note: copy and orig will both be set to 1 if the incoming data is fla gged as professional, or if the receiver is not in use. 11.14 receiver error (10h) (read only) this register contains the aes3 receiver and pll status bits. unmasked bits will go high on occurren ce of the error, and will stay high until the regist er is read. reading the regist er resets all bits to 0, unl ess the error source is still true. bits that are masked off in the receiver error mask regist er will always be 0 in this register. qcrc - q-subcode data crc error indicator. updated on q-subcode block boundaries 0 - no error 1 - error ccrc - channel status block cyclic redundancy check bit. updated on cs block boundaries, valid in pro mode. 0 - no error 1 - error unlock - pll lock status bit. updated on cs block boundaries. 0 - pll locked 1 - pll out of lock v - received aes3 validity bit stat us. updated on sub- frame boundaries. 0 - data is valid and is no rmally linear coded pcm audio 1 - data is invalid, or ma y be valid compressed audio conf - confidence bit. updated on sub-frame boundaries. 0 - no error 1 - confidence error. this is the logical or of bip and unlock. bip - bi-phase error bit. updated on sub-frame boundaries. 0 - no error 1 - bi-phase error. this indicates an error in the received bi-phase coding. par - parity bit. updated on sub-frame boundaries. 0 - no error 1 - parity error 7 6 543210 0 qcrc ccrc unlock v conf bip par
cs8427 36 ds477f1 11.15 receiver error mask (11h) the bits in this register serve as masks for the correspondi ng bits of the receiver error register. if a mask bit is set to 1, the error is unmasked, meaning that its occurrence will appear in the receiver erro r register, will affect the rerr pin, will affect the rerr interrupt, and will affect the current audi o sample according to the status of the hold bit. if a mask bit is set to 0, the error is ma sked, meaning that it s occurrence will not appear in the receiver error register, will not affect the rerr pin, will not a ffect the rerr interrupt, and will not af fect the current audio sample. the ccrc and qcrc bits behave differently fr om the other bits: they do not affect the current audio sample even when unmasked. this register defaults to 00h. 11.16 channel status data buffer control (12h) bsel - selects the data buffer register addresse s to contain user data or channel status data default = ?0? 0 - data buffer address space contains channel status data 1 - data buffer address space contains user data cbmr - control for the first 5 bytes of channel status ?e? buffer default = ?0? 0 - allow d to e buffer transfers to overwr ite the first 5 bytes of channel status data 1 - prevent d to e buffer transfers from over writing first 5 bytes of channel status data detci - d to e c-data buffer transfer inhibit bit. default = ?0? 0 - allow c-data d to e buffer transfers 1 - inhibit c-data d to e buffer transfers eftci - e to f c-data buffer transfer inhibit bit. default = ?0? 0 - allow c-data e to f buffer transfers 1 - inhibit c-data e to f buffer transfers cam - c-data buffer control port access mode bit default = ?0? 0 - one byte mode 1 - two byte mode chs - channel select bit default = ?0? 0 - channel a information is displayed at the emph pin and in the receiver channel status register. channel a information is output during control port reads when cam is set to 0 (one byte mode) 1 - channel b information is displayed at emph pin and in the receiver channel status register. channel b informat ion is output during control port reads when cam is set to 0 (one byte mode) 7 6 543210 0 qcrcm ccrcm unlockm vm confm bipm parm 7 6 543210 0 0 bsel cbmr detci eftci cam chs
cs8427 ds477f1 37 11.17 user data buffer control (13h) ud - user data pin (u) direction specifier if this bit is cha nged during normal operation, then always stop the cs8427 first (run = 0), write the new value, then start the cs8427 (run = 1). default = ?0? 0 - the u pin is an input. the u data is latched in on both rising and falling edges of olrck. this setting also chooses the u pin as the source for transmitted u data. 1 - the u pin is an output. the received u data is clocked out on both rising and falling edges of ilrck. this setting also chooses the u da ta buffer as the source of transmitted u data. ubm1:0 - sets the operating mode of the aes3 u bit manager default = ?00? 00 - transmit all zeros mode 01 - block mode 10 - reserved 11 - reserved detui - d to e u-data buffer transfer inhibit bit (valid in block mode only). default = ?0? 0 - allow u-data d to e buffer transfers 1 - inhibit u-data d to e buffer transfers eftui - e to f u-data buffer transfer inhibit bit (valid in block mode only). default = ?0? 0 - allow u-data e to f buffer transfers 1 - inhibit u-data e to f buffer transfer 11.18 q-channel subcode bytes 0 to 9 (14h - 1dh) (read only) the following 10 registers contain the decoded q-channel subcode data each byte is lsb first with respect to the 80 q-subc ode bits q[79:0]. thus bit 7 of address 14h is q[0] while bit 0 of address 14h is q[7]. similarly bit 0 of address 1dh corresponds to q[79]. 7 6 543210 0 0 0 ud ubm1 ubm0 detui eftui 7 6 543210 control control control control address address address address track track track track track track track track index index index index index index index index minute minute minute minute minute minute minute minute second second second second second second second second frame frame frame frame frame frame frame frame zero zero zero zero zero zero zero zero abs minute abs minute abs minut e abs minute abs minute abs minute abs minute abs minute abs second abs second abs second abs secon d abs second abs second abs second abs second abs frame abs frame abs frame abs frame abs frame abs frame abs frame abs frame
cs8427 38 ds477f1 11.19 omck/rmck ratio (1eh) (read only) this register allows the calculation of the incoming sample rate by the host microcontroller from the equation orr=fso/fsi. the fso is determined by omck, whose frequency is assumed to be 256 fso. orr is represented as an unsigned 2-bit inte ger and a 6-bit fractional part. the value is mean- ingful only after the pll has reached lock. for ex ample, if the omck is 12.288 mhz, fso would be 48 khz (48 khz = 12.288 mhz/256). then if the input sample rate is also 48 khz, you would get 1.0 from the orr register.(the value fr om the orr register is hexadecimal, so the actual value you will get is 40h). if f so /f si > 3 63 / 64 , orr will saturate at the value ffh. also, there is no hysteresis on orr. therefore a small am ount of jitter on either clock can cause the lsb orr[0] to oscillate. orr7:6 - integer part of the ratio (integer value=in teger(srr[7:6])) orr5:0 - fractional part of the ratio (fraction value=integer(srr[5:0])/64) 11.20 c-bit or u-bit data buffer (20h - 37h) either channel status data buffer e or user data buffer e (provided ubm bits are set to block mode) is accessible using these register addresses. 11.21 cs8427 i.d. and version register (7fh) (read only) id3:0 - id code for the cs8427. permanently set to 0111 ver3:0 - cs8427 revision level. revision a is coded as 0001 7 6 543210 orr7 orr6 orr5 orr4 orr3 orr2 orr1 orr0 7 6 543210 id3 id2 id1 id0 ver3 ver2 ver1 ver0
cs8427 ds477f1 39 12. pin description - software mode sda/cdout ad0/cs emph rxp rxn va+ agnd filt rst rmck rerr ilrck isclk sdin 28 27 *26 *25 *24 *23 *22 21 20 19 *18 *17 *16 *15 1 2 3+ 4* 5* 6* 7* 8* 9* 10* 11* 12* 13* 14* scl/cclk ad1/cdin txp txn h/s v+ dgnd omck u int sdout olrck osclk tcbl * pins which remain the same function in all modes. + pins which require a pull up or pull down resistor to select the desired startup option. l sda/cdout 1 serial control data i/o (i2c) / data out (spi) ( input/output ) - in i2c mode, sda is the con- trol i/o data line. sda is open drain and require s an external pull-up resistor to vl+. in spi mode, cdout is the output data from th e control port interface on the cs8427 ad0/cs 2 address bit 0 (i2c) / control port chip select (spi) ( input) - a falling edge on this pin puts the cs8427 into spi control po rt mode. with no falling edge, the cs8427 defaults to i2c mode. in i2c mode, ad0 is a chip address pin. in spi mode, cs is used to enable the control port interface on the cs8427 emph 3 pre-emphasis ( output ) - emph is low when the incoming ch annel status data indicates 50/15 ms pre-emphasis. emph is high when the channel status data indicates no pre- emphasis or indicates pre-emphasis other than 50/15 ms. this is also a start-up option pin, and requires a 47 kw resistor to either vl+ or dgnd, which determines the ad2 address bit for the control port in i2c mode rxp rxn 4 5 differential line receiver ( input ) - receives differential aes3 data. va+ 6 positive analog power ( input ) - positive supply for the chip?s analog section. nominally +5.0 v. this supply should be as quiet as possib le since noise on this pin will directly affect the jitter performance of the recovered clock agnd 7 analog ground ( input ) - ground for the analog section. agnd should be connected to the same ground as dgnd filt 8 pll loop filter ( output ) - an rc network should be connected between this pin and ground. see ?appendix c: pll filter? on page 54 for recommended schematic and compo- nent values. rst 9 reset ( input ) - when rst is low, the cs8427 enters a low power mode and all internal states are reset. on initial power up, rst must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. this is particularly true in hardware mode with multiple cs8427 devices where syn chronization between devices is important rmck 10 input section recovered master clock ( input / output ) - input section recovered master clock output when pll is used. frequency defaults to 256x the sample rate (fs) and may be set to 128x. when the pll is bypassed by the rxd[1:0] bits in the clock source control reg- ister, an external clock of 256 fs may be applied to this pin
cs8427 40 ds477f1 rerr 11 receiver error ( output ) - when high, indicate s an error condition fr om the aes3 receiver. the status of this pin is updated once per su b-frame of incoming aes3 data. conditions that can cause rerr to go high are: validity, parity error, bi-phase coding error, confidence, as well as loss of lock by the pl l. each condition may be optionally masked from affecting the rerr pin using the receiver er ror mask register. the rerr pin tracks the status of the unmasked errors: the pin goes high as soon as an unmasked error occurs and goes low immediately when all unm asked errors go away. ilrck 12 serial audio input left/right clock ( input / output ) - word rate clock for the audio data on the sdin pin. isclk 13 serial audio bit clock ( input / output ) - serial bit clock for audio data on the sdin pin. sdin 14 serial audio data port ( input ) - audio data serial input pin. tcbl 15 transmit channel status block start ( input / output ) - when operated as output, tcbl is high during the first sub-frame of a transmitted channel status block, and low at all other times. when operated as input, driving tcbl high for at least three omck clocks will cause the next transmitted sub-frame to be the start of a channel status block. osclk 16 serial audio ou tput bit clock ( input / output ) - serial bit clock for audio data on the sdout pin olrck 17 serial audio output left/right clock ( input / output ) - word rate clock for the audio data on the sdout pin. frequency will be the output sample rate (fs) sdout 18 serial audio output data ( output ) - audio data serial output pin int 19 interrupt ( output ) - indicates errors and key events du ring the operation of the cs8427. all bits affecting int may be unmasked through bits in the control registers. the condition(s) that initiated interrupt are readable through a co ntrol register. the polarity of the int output, as well as selection of a standard or open drai n output, is set through a control register. once set true, the int pin goes false only after the interrupt status registers have been read and the interrupt status bits have returned to zero u 20 user data (input/ output ) - may optionally be used to input user bit data for transmission by the aes3 transmitter, se e figure 13 on page 22 for timing information. alternatively, the u pin may be set to output user data from the aes3 receiver, see figure 13 on page 22 for tim- ing information. if not driven, a 47 kw pull-down resistor is recommended for the u pin, since the default state of the ud direction bit sets the u pin as an input. the pull-down resistor ensures that the transmitted user data will be ze ro. if the u pin is always set to be an output, thereby causing the u bit manager to be the sour ce of the u data, then the resistor is not necessary. the u pin should not be tied directly to ground, in case it is programmed to be an output, and subsequently tries to output a logic high. this sit uation may affect the long term reliability of the device. if the u pin is driven by a logic level output, then a 100 w series resistor is recommended. omck 21 system clock ( input ) - when the omck system clock mode is enabled by the swclk bit in the control 1 register, the clock signal input on this pin is output through rmck. omck serves as reference signal for omck/r mck ratio expressed in register 1eh. dgnd 22 digital ground ( input ) - ground for the digital section. dgnd should be connected to the same ground as agnd vl+ 23 positive digital power ( input ) - typically +3.3 v or +5.0 v. h/s 24 hardware/software mode control ( input ) - determines the method of controlling the oper- ation of the cs8427, and the method of accessing cs and u data. in software mode, device control and cs and u data access is primarily through the control port, using a microcontrol- ler. hardware mode provides an alternate mode of operation and access to the cs and u data through dedicated pins. this pin should be permanently tied to vl+ or dgnd
cs8427 ds477f1 41 txp txn 25 26 differential line driver ( output ) - drivers transmit aes3 data and are pulled low while the cs8427 is in the reset state. ad1/cdin 27 address bit 1 (i2c) / serial control data in (spi) ( input ) - in i2c mode, ad1 is a chip address pin. in spi mode, cdin is the inpu t data line for the co ntrol port interface scl/cclk 28 control port clock ( input ) - serial control interface clock and is used to clock control data bits into and out of the cs8427. in i2c mode, scl requires an external pull-up resistor to vl+
cs8427 42 ds477f1 13. hardware mode description hardware mode is selected by connecting the h/s pin to ?1?. hardware mode data flow is shown in figure 19 . audio data is input through the aes3 re- ceiver, and routed to the serial audio output port. different audio data synchronous to rmck may be input into the serial audio input port, and output through the aes3 transmitter. the channel status data, user data and validity bit information are handled in 2 alternative modes: a and b, determined by a start-up resistor on the copy pin. in mode a, the received pro, copy, orig, emph , and audio channel status bits are output on pins. the transmitted channel status bits are copied from the received channel status data, and the transmitted u and v bits are 0. in mode b, only the copy and orig pins are out- put, and reflect the received channel status data. the transmitted channel status bits, user data and validity bits are input serially through the pro/c, emph /u and audio /v pins. figure 13 on page 22 shows the timing requirements. the apms pin allows the serial audio input port to be set to master or slave. if a validity, parity, bi-phase or lock receiver error occurs, the current audio sample is passed un- modified to the serial audio output port. start-up options are shown in table 2 on page 43 , and allow choice of the serial audio output port as a master or slave, whether tcbl is an input or an output, the audio serial ports formats and the source of the transmitted c, u and v data. 13.1 serial audio port formats in hardware mode, only a limited number of alter- native serial audio port formats are available. these formats are described by table 3 on page 43 and table 4 on page 43 , which define the equivalent software mode bit settings for each for- mat. timing diagrams are shown in figure 15 on page 23 and figure 16 on page 24 . aes3 encoder &tx serial audio output aes3 rx & decoder c&ubitdatabuffer rxp rxn olrck osclk sdout txp txn rmck rerr copy orig emph/u audio/v tcbl vl+ h/s power supply pins (vd+, va+, dgnd, agnd) & the reset pin (rst) and the pll filter pin (filt) are omitted from this diagram. please refer to the typical connection diagram for hook-up details. serial audio input ilrck isclk sdin pro/c apms figure 19. hardware mode
cs8427 ds477f1 43 sdout rmck rerr orig copy function lo - - -- serial output port is slave hi - - -- serial output port is master --- -lo mode a: c transmitted data is copied from received data, u and v =0, received pro, emph , audio is visible --- -hi mode b: cuv transmitted data is input serially on pins, received pro, emph and audio is not visible -lolo -- serial input & output format: left justified -lohi -- serial input & output format: i2s -hilo -- serial input & output format: right justified -hihi -- serial input format: left justified, output format: aes3 direct --- lo - tcbl is an input --- hi - tcbl is an output table 2. hardware mo de start-up options sosf sores1/0 sojust sodel sospol solrpol of1 - left justified 0 00 0 0 0 0 of2 - i2s 24-bit data 0 00 0 1 0 1 of3 - right justified, master mode only 0 00 1 0 0 0 of4 - i2s 16 bit data 0 10 0 1 0 1 of5 - direct aes3 data 0 11 0 0 0 0 table 3. serial audio output formats available in hardware mode sisf sires1/0 sijust sidel sispol silrpol if1 - left justified 0 00 0 0 0 0 if2 - i2s 0 00 0 1 0 1 if3 - right justified 24-bit data 0 00 1 0 0 0 if4 - right justified 16-bit data 0 10 1 0 0 0 table 4. serial audio input formats available in hardware mode
cs8427 44 ds477f1 14. pin description - hardware mode * pins which remain the same function in all modes. + pins which require a pull up or pull down resistor to select the desired startup option. copy dgnd2 emph/u rxp rxn va+ agnd filt rst rmck rerr ilrck isclk sdin +28 27 *26 *25 *24 *23 *22 21 20 19 +*18 *17 *16 *15 1+ 2 3 4* 5* 6* 7* 8* 9* 10*+ 11*+ 12* 13* 14* orig v2+ txp txn h/s v+ dgnd apms pro/c audio/v sdout olrck osclk tcbl l l copy 1 copy channel status bit ( output ) - reflects the state of the co pyright channel status bit in the incoming aes3 data stream. if the category code is set to general, copyright will be indi- cated whatever the state of the copyright bit. this is also a start-up option pin, and requires a pull-up or pull-down resistor. dgnd2 dgnd 2 22 digital ground ( input ) - ground for the digital section. dgnd should be connected to the same ground as agnd. emph/ u 3 pre-emphasis indicator / u-bit ( input / output ) - the emph /u pin either reflects the state of the emph channel status bit in the in coming aes3 data stream, or is the serial u-bit input for the aes3 transmitted data, clocked by olrck. if i ndicating emphasis: emph /u is low when the incoming channel status data indicates 50/15 ms pre-emphasis. emph /u is high when the channel status data indicates no pre-emphasis or indicates pre-emphasis other than 50/15 ms. rxp rxn 4 5 differential line receiver ( input ) - receives differential aes3 data. va+ 6 positive analog power ( input ) - positive supply for the analog section. nominally +5.0 v. this supply should be as quiet as possible sinc e noise on this pin will directly affect the jitter performance of the recovered clock agnd 7 analog ground ( input ) - ground for the analog section. agnd should be connected to the same ground as dgnd filt 8 pll loop filter ( output ) - an rc network should be connected between this pin and ground. see ?appendix c: pll filter? on page 54 for recommended schematic and component values. rst 9 reset ( input ) - when rst is low, the cs8427 enters a low power mode and all internal states are reset. on initial power up, rst must be held low until the po wer supply is stable, and all input clocks are stable in frequency and phase. this is particularly true in hardware mode with multiple cs8427 devices where synchronization between devices is important rmck 10 input section recovered master clock ( output ) - input section recovered master clock out- put when pll is used. frequency is 256x the sample rate (fs). rerr 11 receiver error ( output ) - when high, indicates an error in the operation of the aes3 receiver. the status of this pin is updated once per sub- frame of incoming aes3 data. conditions that can cause rerr to go high are: parity error, bi-phase coding error, confidence, as well as loss of lock by the pll.
cs8427 ds477f1 45 ilrck 12 serial audio input left/right clock ( input / output ) - word rate clock for the audio data on the sdin pin. isclk 13 serial audio bit clock ( input / output ) - serial bit clock for audio data on the sdin pin. sdin 14 serial audio data port ( input ) - audio data serial input pin. tcbl 15 transmit channel status block start ( input / output ) - when operated as output, tcbl is high during the first sub-frame of a transmitted cha nnel status block, and low at all other times. when operated as i nput, driving tcbl high for at least three omck clocks will cause the next transmitted sub-frame to be the start of a channel status block. osclk 16 serial audio output bit clock ( input / output ) - serial bit clock for audio data on the sdout pin olrck 17 serial audio output left/right clock ( input / output ) - word rate clock for the audio data on the sdout pin. frequency will be the output sample rate (fs) sdout 18 serial audio output data ( output ) - audio data serial output pin audio /v 19 audio channel status bit / v-bit ( input / output ) - reflects either the state of the audio/non- audio channel status bit in the incoming aes3 data stream or is the validity bit data input for the aes3 transmitted data stream, clocke d by olrck. pro/c 20 pro channel status bit / c-bit ( input / output ) - reflects either the state of the profes- sional/consumer channel status bi t in the incoming aes3 data st ream or is the serial c-bit input for the aes3 transmitte d data, clocked by olrck. apms 21 serial audio input port master/slave select ( input ) - apms should be connected to vl+ to set serial audio input port as a master, or co nnected to dgnd to set the port as a slave. vl+ vl2+ 23 27 positive digital power ( input ) - typically +3.3 v or +5.0 v. h/s 24 hardware/software mode control ( input ) - determines the method of controlling the opera- tion of the cs8427, and the method of access ing cs and u data. in software mode, device control and cs and u data access is primarily th rough the control port, using a microcontroller. hardware mode provides an alternate mode of operation and access to the cs and u data through dedicated pins. this pin should be permanently tied to vl+ or dgnd txp txn 25 26 differential line driver ( output ) - drivers transmit aes3 data and are pulled low while the cs8427 is in the reset state. orig 28 orig channel status bit ( output ) - scms generation indicator. this is decoded from the incoming category code and the l bit. a low output indicates that the source of the audio data stream is a copy. a high indicates that the s ource of the audio data stream is an original recording. this is also a start-up option pin, and requires a pull-up or pull-down resistor.
cs8427 46 ds477f1 15. applications 15.1 reset, power down and start-up when rst is low, the cs8427 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are mut- ed. when rst is high, the control port becomes operational and the desired settings should be loaded into the control registers. writing a 1 to the run bit will then cause the part to leave the low power state and begin operation. after the pll has settled, the aes3 and serial audio outputs will be enabled. some options within the cs8427 are controlled by a start-up mechanism. during the reset state, some of the output pins are reconfigured internally to be inputs. immediately upon exiting the reset state, the level of these pins is sensed. the pins are then switched to be outputs. this mechanism allows output pins to be used to set alternative modes in the cs8427 by connecting a 47 k ? resis- tor to between the pin and either vl+ (hi) or dgnd (lo). for each mode, every start-up option select pin must have an external pull-up or pull-down re- sistor. in software mode, the only start-up option pin is emph , which is used to set a chip address bit for the control port in i2c mode. hardware modes use many start-up options, which are de- tailed in the hardware definition section at the end of this data sheet. 15.2 id code and revision code the cs8427 has a register that contains a four bit code to indicate that the addressed device is a cs8427. this is useful when other cs84xx family members are resident in the same system, allow- ing common software modules. the cs8427 four bit revi sion code is also avail- able. this allows the software driver for the cs8427 to identify which revision of the device is in a particular system, and modify its behavior ac- cordingly. to allow for future revisions, it is strongly recommend that the revision code is read into a variable area within the microcontroller, and used wherever appropriate as revision details become known. 15.3 power supply, grounding, and pcb layout for most applications, the cs8427 can be operat- ed from a single +5.0 v supply, following normal supply decoupling practices, see figure 5 on page 11 . note that the i2c protocol is supported only in vl+ = 5.0 v mode. for applications where the re- covered input clock, output on the rmck pin, is re- quired to be low jitter, then use a separate, quiet, analog +5.0 v supply for va+, decoupled to agnd. in addition, a separate region of analog ground plane around the filt, agnd, va+, rxp, and rxn pins is recommended. the vl+ supply should be well decoupled with a 0.1 f capacitor to dgnd to minimize aes3 trans- mitter induced transients. extensive use of power and ground planes, ground plane fill in unused areas and surface mount de- coupling capacitors are recommended. decou- pling capacitors should be mounted on the same side of the board as the cs8427 to minimize induc- tance effects, and all decoupling capacitors should be as close to the cs8427 as possible. 15.4 synchronization of multiple cs8427s the serial audio output ports of multiple cs8427s can be synchronized if all devices share the same master clock, osclk, olrck, and rst line and leave the reset state on the same master clock fall- ing edge. either all the ports need to be in slave mode, or one can be set as a master. multiple aes3 transmitters can be synchronized if all devices share the same master clock, tcbl, and rst signals and leave the reset state on the same master clock falling edge. the tcbl pin is used to synchronize mu ltiple cs8427 aes3 trans- mitters at the channel status block boundaries. one cs8427 must have its tcbl set to master; the others must be set to slave tcbl. alternative- ly, tcbl can be derived from external logic, in which case all the cs8427 devices should be set to slave tcbl.
cs8427 ds477f1 47 16. package dimensions inches millimeters dim min nom max min nom max a 0.093 0.098 0.104 2.35 2.50 2.65 a1 0.004 0.008 0.012 0.10 0.20 0.30 b 0.013 0.017 0.020 0.33 0.42 0.51 c 0.009 0.011 0.013 0.23 0.28 0.32 d 0.697 0.705 0.713 17.70 17.90 18.10 e 0.291 0.295 0.299 7.40 7.50 7.60 e 0.040 0.050 0.060 1.02 1.27 1.52 h 0.394 0.407 0.419 10.00 10.34 10.65 l 0.016 0.026 0.050 0.40 0.65 1.27 0 4 8 0 4 8 jedec #: ms-013 controlling dimension is millimeters 28l soic (300 mil body) package drawing d h e b a1 a c l seating plane 1 e
cs8427 48 ds477f1 notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion /intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximu m material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a----0.47----1.20 a1 0.002 0.004 0.006 0.05 0.10 0.15 a2 0.03150 0.035 0.04 0.80 0.90 1.00 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.378 bsc 0.382 bsc 0.386 bsc 9.60 bsc 9.70 bsc 9.80 bsc 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.65 bsc -- l 0.020 0.024 0.029 0.50 0.60 0.75 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. 28l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs8427 ds477f1 49 17. appendix a: external aes3/spdif/iec60958 transmitter and receiver components this section details the external components re- quired to interface the aes3 transmitter and re- ceiver to cables and fiber-optic components. 17.1 aes3 transmitter external components the output drivers on the cs8427 are designed to drive both the professional and consumer interfac- es. the aes3 specification for professional/broad- cast use calls for a 110 ? source impedance and a balanced drive capability . since the transmitter output impedance is very low, a 110 ? resistor should be placed in series with one of the transmit pins. the specifications call for a balanced output drive of 2-7 v peak-to-peak into a 110 ? load with no cable attached. using the circuit in figure 20 , the output of the transformer is short-circuit pro- tected, has the proper source impedance, and pro- vides a 5 v peak-to-peak signal into a 110 ? load. lastly, the two output pins should be attached to an xlr connector with male pins and a female shell, and with pin 1 of the connector grounded. in the case of consumer use, the iec60958 speci- fications call for an unbalanced drive circuit with an output impedance of 75 ? and a output drive level of 0.5 v peak-to-peak 20% when measured across a 75 ? load using no cable. the circuit shown in figure 21 only uses the txp pin and pro- vides the proper output impedance and drive level using standard 1% resistors. if vl+ is driven from +3.3 v, use resistor values of 243 ? and 107 ? . the connector for a consumer application would be an rca phono socket. this circuit is also short circuit protected. the txp pin may be used to drive ttl or cmos gates as shown in figur e 22. this circuit may be used for optical connectors for digital audio since they usually have ttl or cmos compatible inputs. this circuit is also useful when driving multiple dig- ital audio outputs since rs422 line drivers have ttl compatible inputs. 17.2 isolating transformer requirements please refer to the application note an134: aes and spdif recommended transformers for re- sources on transformer selection. 110-(r txp +r txn ) txp txn xlr 1 cs8427 figure 20. professional output circuit figure 21. consumer output circuit 374-r txp 90.9 ? txp txn rca phono cs8427 figure 22. ttl/cmos output circuit txp txn ttl or cmos gate cs8427
cs8427 50 ds477f1 17.3 aes3 receiver external components the cs8427 aes3 receiver is designed to accept both the professional and consumer interfaces. the digital audio specifications for professional use call for a balanced receiver, using xlr con- nectors, with 110 ? 20% impedance. the xlr connector on the receiver should have female pins with a male shell. since the receiver has a very high input impedance, a 110 ? resistor should be placed across the receiver terminals to match the line impedance, as shown in figure 23 . although transformers are not required by the aes, they are, however, strongly recommended. if some isolation is desired without the use of trans- formers, a 0.01 f capacitor should be placed in series with each input pin (rxp and rxn) as shown in figure 24 . however, if a transformer is not used, high frequency energy could be coupled into the receiver, causing degradation in analog performance. figure 23 and figure 24 show an optional dc blocking capacitor (0.1 f to 0.47 f) in series with the cable input. this improves the robustness of the receiver, preventing the saturation of the transformer, or any dc current flow, if a dc voltage is present on the cable. in the configuration of systems, it is important to avoid ground loops and dc current flowing down the shield of the cable that could result when boxes with different ground potentials are connected. generally, it is good practice to ground the shield to the chassis of the transmitting unit, and connect the shield through a capacitor to chassis ground at the receiver. however, in some cases it is advan- tageous to have the ground of two boxes held to the same potential, and the cable shield might be depended upon to make that electrical connection. generally, it may be a good idea to provide the op- tion of grounding or capacitively coupling the shield to the chassis. in the case of the consumer interface, the stan- dards call for an unbalanced circuit having a re- ceiver impedance of 75 ? 5%. the connector for the consumer interface is an rca phono socket. the receiver circuit for the consumer interface is shown in figure 25 . the circuit shown in figure 26 may be used when external rs422 receivers, optical receivers or oth- er ttl/cmos logic outputs drive the cs8427 re- ceiver section. 17.4 isolating transformer requirements please refer to the application note an134: ?aes and spdif recommended transformers? for re- sources on transformer selection 1 xlr twisted pair 110 ? 110 ? cs8427 rxp rxn 0.01 f 0.01 f * see text figure 23. professional input circuit figure 24. transformerless professional input circuit 1 xlr twisted pair 110 ? 110 ? cs8427 rxp rxn 0.01 f 0.01 f *seetext rca phono rxp rxn cs8427 coax 75 ? 75 ? 0.01 f 0.01 f figure 25. consumer input circuit figure 26. ttl/cmos input circuit rxp rxn cs8427 0.01 f 0.01 f ttl/cmos gate
cs8427 ds477f1 51 18. appendix b: channel status and user data buffer management the cs8427 has a comprehensive channel status (c) and user (u) data buffering scheme, which al- lows automatic management of channel status blocks and user data. alternatively, sufficient con- trol and access is provided to allow the user to completely manage the c and u data through the control port. be aware that the run bit should be set to 1 in order to access the c and u data buffer through the control port. 18.1 aes3 channel status(c) bit management the cs8427 contains sufficient ram to store a full block of c data for both a and b channels (192x2 = 384 bits), and also 384 bits of u information. the user may read from or write to these rams through the control port. the cs8427 manages the flow of channel status data at the block level, meaning that entire blocks of channel status information are buffered at the in- put, synchronized to the output timebase, and then transmitted. the buffering scheme involves a cas- cade of 3 block-sized buffers, named d,e and f, as shown in figure 27 . the msb of each byte repre- sents the first bit in the serial c data stream. for example, the msb of byte 0 (which is at control port address 20h) is the consumer/professional bit for channel status block a. the first buffer, d, accepts incoming c data from the aes receiver. the 2nd buffer, e, accepts entire blocks of data from the d buffer. the e buffer is also accessible from the control port, allowing read and writing of the c data. the 3rd buffer (f) is used as the source of c data for the aes3 transmitter. the f buffer accepts block transfers from the e buffer. 18.1.1 manually accessing the e buffer the user can monitor the data being transferred by reading the e buffer, which is mapped into the reg- ister space of the cs8427, through the control port. the user can modify the data to be transmitted by writing to the e buffer. the user can configure the interrupt enable regis- ter to cause interrupts to occur whenever ?d to e? or ?e to f? buffer transfers occur. this allows deter- mination of the allowable time periods to interact with the e buffer. also provided are ?d to e? and ?e to f? inhibit bits. the associated buffer trans fer is disabled whenev- er the user sets these bits. these may be used whenever ?long? control port interactions are oc- curring. they can also be used to align the behav- ior of the buffers with the selected audio data flow. for example, if the audio data flow is serial port in to aes3 out, then it is necessary to inhibit ?d toe? transfers, since these would overwrite the desired transmit c data with invalid data. flowcharts for reading and writing to the e buffer are shown in figure 28 and figure 29 . for reading, since a d to e interrupt just occurred, then there a substantial time interval until the next d to e trans- fer (approximately 24 frames worth of time). this is usually plenty of time to access the e data without having to inhibit the next transfer. control port from aes3 receiver to aes3 transmitter e 24 words 8-bits 8-bits ab df received data buffer transmit data buffer figure 27. channel status data buffer structure
cs8427 52 ds477f1 for writing, the sequence starts after a e to f trans- fer, which is based on the output timebase. since a d to e transfer could occur at any time (this is based on the input timebase), then it is important to inhibit d to e transfers while writing to the e buff- er until all writes are complete. then wait until the next e to f transfer occurs before enabling d to e transfers. this ensures that the data written to the e buffer actually gets transmitted and not overwrit- ten by a d to e transfer. if the channel status block to transmit indicates pro mode, then the crcc byte is automatically calculated by the cs8427, and does not have to be written into the last byte of the block by the host mi- crocontroller. 18.1.2 reserving the firs t 5 bytes in the e buffer d to e buffer transfers periodically overwrite the data stored in the e buffer. this can be a problem for users who want to transmit certain channel sta- tus settings which are different from the incoming settings. in this case, the user would have to su- perimpose his settings on the e buffer after every d to e overwrite. to avoid this problem, the cs8427 has the capa- bility of reserving the first 5 bytes of the e buffer for user writes only. when this capability is in use, in- ternal d to e buffer transfers will not affect the first 5 bytes of the e buffer. therefore, the user can set values in these first 5 e bytes once, and the set- tings will persist until the next user change. this mode is enabled by the channel status data buff- er control register. 18.1.3 serial copy management system (scms) in software mode, the cs8427 allows read/modi- fy/write access to all the channel status bits. for consumer mode scms compliance, the host mi- crocontroller needs to read and manipulate the category code, copy bit and l bit appropriately. in hardware mode, the scms protocol can be fol- lowed by either using the copy and orig input pins, or by using the c bit serial input pin. these options are documented in the hardware mode section of this data sheet. 18.1.4 channel status data e buffer access the e buffer is organized as 24 x 16-bit words. for each word the ms byte is the a channel data, and the ls byte is the b channel data (see figure 27 ). there are two methods of accessing this memory, known as one byte mode and two byte mode. the desired mode is selected through a control register bit. one byte mode in many applications, the channel status blocks for the a and b channels will be identical. in this situ- ation, if the user reads a byte from one of the chan- nel's blocks, the corresponding byte for the other channel will be the same. similarly, if the user wrote a byte to one channel's block, it would be necessary to write the same byte to the other block. one byte mode takes advantage of the often identical nature of a and b channel status data. figure 28. flowchart for reading the e buffer d to e interrupt occurs optionally set d to e inhibit read e data if set, clear d to e inhibit return e to f interrupt occurs optionally set e to f inhibit clear d to e inhibit if set, clear e to f inhibit return set d to e inhibit write e data wait for e to f transfer figure 29. flowchart for writing the e buffer
cs8427 ds477f1 53 when reading data in one byte mode, a single byte is returned, which can be from channel a or b data, depending on a register control bit. if a write is be- ing done, the cs8427 expects a single byte to be input to its control port. this byte will be written to both the a and b locations in the addressed word. one byte mode saves the user substantial control port access time, as it effectively accesses 2 bytes worth of information in 1 byte's worth of access time. if the control port's autoincrement addressing is used in combination with this mode, multi-byte accesses such as full-block reads or writes can be done especially efficiently. two byte mode there are those applications in which the a and b channel status blocks will not be the same, and the user is interested in accessing both blocks. in these situations, two byte mode should be used to access the e buffer. in this mode, a read will cause the cs8427 to out- put two bytes from its control port. the first byte out will represent the a channel status data, and the 2nd byte will represent the b channel status data. writing is similar, in that two bytes must now be in- put to the cs8427's control port. the a channel status data is first, b channel status data second. 18.2 aes3 user (u) bit management the cs8427 u bit manager has two operating modes: transmit all zeros and block mode. 18.2.1 mode 1: transmit all zeros mode 1 causes only zeros to be transmitted in the output u data, regardless of e buffer contents or u data embedded in an input aes3 data stream. this mode is intended for the user who does not want to transceive u data, and simply wants the output u channel to contain no data. 18.2.2 mode 2: block mode mode 2 is very similar to the scheme used to con- trol the c bits. entire blocks of u data are buffered from input to output, using a cascade of 3 block- sized rams to perform the buffering. the user has access to the second of these 3 buffers, denoted the e buffer, through the control port. block mode is designed for use in aes3 in, aes3 out situations in which input u data is decoded using a microcon- troller through the control port. it is also the only mode in which the user can merge his own u data into the transmitted aes3 data stream. the u buffer access only operates in two byte mode, since there is no concept of a and b blocks for user data. the arrangement of the data is as fol- lows:bit15[a7]bit14[b7]bit13[a6]bit12[b6]...bit1[a 0]bit0[b0]. the arrangement of the data in the each byte is that the msb is the first received bit and is the first transmitted bit. the first byte read is the first byte received, and the first byte sent is the first byte transmitted. if you read two bytes from the e buffer, you will get the following arrangement: a[7]b[7]a[6]b[6]....a[0]b[0].
cs8427 54 ds477f1 19. appendix c: pll filter 19.1 general an on-chip phase locked loop (pll) is used to re- cover the clock from the incoming data stream. figure 30 is a simplified diagram of the pll in these parts. when the pll is locked to an aes3 in- put stream, it is updated at each preamble in the aes3 stream. this occurs at twice the sampling frequency, f s . when the pll is locked to ilrck, it is updated at f s so that the duty cycle of the input doesn?t affect jitter. there are some applications where low jitter in the recovered clock, presented on the rmck pin, is important. for this reason, the pll has been de- signed to have good jitter attenuation characteris- tics, as shown in figure 33, figure 34, figure 35, and figure 36. in addition, the pll has been de- signed to only use the preambles of the aes3 stream to provide lock update information to the pll. this results in the pll being immune to data dependent jitter affects because the aes3 pream- bles do not vary with the data. the pll has the ability to lock onto a wide range of input sample rates with no external component changes. if the sample rate of the input subse- quently changes, for exam ple in a varispeed appli- cation, the pll will only track up to 12.5% from the nominal center sample rate. the nominal cen- ter sample rate is the sample rate that the pll first locks onto upon applicat ion of an aes3 data stream or after enabling the cs8415a clocks by setting the run control bit. if the 12.5% sample rate limit is exceeded, the pll will return to its wide lock range mode and re-acquire a new nominal center sample rate. phase comparator and charge pump n vco rmck input c rip c filt r filt figure 30. pll block diagram
cs8427 ds477f1 55 19.2 external filter components 19.2.1 general the pll behavior is affected by the external filter component values. figure 5 on page 11 shows the recommended configuration of the two capacitors and one resistor that comprise the pll filter. in table 7 and table 8, the component values shown for the 32 to 96 khz range have the highest corner frequency jitter attenuation curve, takes the short- est time to lock, and offers the best output jitter per- formance. the component values shown in table 6 and table 8 for the 8 to 96 khz range al- lows the lowest input sample rate to be 8 khz, and increases the lock time of the pll. lock times are worst case for an fsi transition of 96 khz. 19.2.2 capacitor selection the type of capacitors used for the pll filter can have a significant effect on receiver performance. large or exotic film capacitors are not necessary as their leads and the required longer circuit board traces add undesirable inductance to the circuit. surface mount ceramic capacitors are a good choice because their own inductance is low, and they can be mounted close to the filt pin to minimize trace inductance. for c rip , a c0g or npo dielectric is recommended, and for c filt , an x7r dielectric is preferred. avoid capacitors with large temperature coefficients, or capacitors with high dielectric constants, that are sensitive to shock and vibration. these include the z5u and y5v dielectrics. 19.2.3 circuit board layout board layout and capacitor choice affect each other and determine the performance of the pll. figure 31 contains a suggested layout for the pll filter components and for bypassing the analog supply voltage. the 0.1 f bypass capacitor is in a 1206 form factor. r filt and the other three capacitors are in an 0805 form factor. the traces are on the top surface of the board with the ic so that there is no via inductance. the traces themselves are short to minimize the inductance in the filter path. the va+ and agnd traces extend back to their origin and are shown only in truncated form in the drawing. va+ agnd filt c filt 1000 pf .1f r filt c rip figure 31. recommended layout example
cs8427 56 ds477f1 19.3 component value selection when transitioning from one revision of the part another, component values may need to be changed. while it is mandatory for customers to change the external pll component values when transitioning from revision a to revision a1 or from revision a to revision a2, customers do not need to change external pll component values when tran- sitioning from revision a1 to revision a2, unless the part is used in an application that is required to pass the aes3 or iec60958-4 specification for re- ceiver jitter tolerance (see table 7). 19.3.1 identifying the part revision the first line of the part marking on the package in- dicates the part number and package type (cs8427-xx). table 5 shows a list of part revisions and their corresponding second line part marking, which indicates what revision the part is. 19.3.2 locking to th e rxp/rxn receiver inputs cs8427 parts that are configured to lock to only the rxp/rxn receiver inputs should use the exter- nal pll component values listed in table 6 and table 7. values listed for the 32 to 96 khz fs range will have the highest corner frequency jitter attenuation curve, take the shortest time to lock, and offer the best output jitter performance. revision pre-october 2002 soic & tssop (10-digit) new soic (12-digit) new tssop (10-digit) a zxxxxxxxxx zfbaaxxxxxxx naaxxxxxxx a1 rxxxxxxxxx rfbaa1xxxxxx naa1xxxxxx a2 n/a rfbaa2xxxxxx naa2xxxxxx table 5. second line part marking revision r filt (k ? )c filt ( f) c rip (nf) pll lock time (ms) a 0.909 1.8 33 56 a1 0.4 0.47 47 60 a2 0.4 0.47 47 60 table 6. locking to rxp/rxn - fs = 8 to 96 khz revision r filt (k ? )c filt ( f) c rip (nf) pll lock time (ms) a* 3.0 0.047 2.2 35 a1* 1.2 0.1 4.7 35 a2 1.2 0.1 4.7 35 a2* 1.6 0.33 4.7 35 table 7. locking to rxp/rxn - fs = 32 to 96 khz * parts used in applications that are required to pass the aes3 or iec60958-4 specification for re- ceiver jitter tolerance should use these component values. please note that the aes3 and iec60958 specifications do not have allow ances for locking to sample rates less than 32 khz or for locking to the ilrck input. also note that m any factors can affect jitter perfo rmance in a system. please follow the circuit and layout recommendations outlined previously.
cs8427 ds477f1 57 19.3.3 locking to the ilrck input cs8427 parts that are configured to lock to the il- rck input should use the external pll component values listed in table 8. note that parts that need to lock to both ilrck and rxp/rxn should use these values. values listed for the 32 to 96 khz fs range will have the highest corner frequency jitter attenuation curve, take the shortest time to lock, and offer the best output jitter performance. 19.3.4 jitter tolerance shown in figure 32 is t he receiver jitter tolerance template as illustrated in the aes3 and iec60958- 4 specification. cs8427 parts used with the appro- priate external pll component values (as noted in table 7) have been tested to pass this template. revision fs range (khz) r filt (k ? )c filt ( f) c rip (nf) pll lock time (ms) a 8 to 96 1.3 2.7 62 120 a 32-96 5.1 0.15 3.9 70 a1/a2 8 to 96 0.3 1.0 100 120 a1/a2 32-96 0.6 0.22 22 70 table 8. locking to the ilrck input figure 32. jitter tolerance template
cs8427 58 ds477f1 19.3.5 jitter attenuation shown in figure 33, figure 34, figure 35, and fig- ure 36 are jitter attenuation plots for the various re- visions of the cs8427 when used with the appropriate external pll component values (as noted in table 7). the aes3 and iec60958-4 specifications do not have allowances for locking to sample rates less than 32 khz or for locking to the ilrck input. these specifications state a max- imum of 2 db jitter gain or peaking. 10 ?1 10 0 10 1 10 2 10 3 10 4 10 5 ?20 ?15 ?10 ?5 0 5 jitter frequency (hz) jitter attenuation (db) 10 ?1 10 0 10 1 10 2 10 3 10 4 10 5 ?20 ?15 ?10 ?5 0 5 jitter frequency (hz) jitter attenuation (db) 10 ?1 10 0 10 1 10 2 10 3 10 4 10 5 ?25 ?20 ?15 ?10 ?5 0 5 jitter frequency (hz) jitter attenuation (db) 10 ?1 10 0 10 1 10 2 10 3 10 4 10 5 ?25 ?20 ?15 ?10 ?5 0 5 jitter frequency (hz) jitter attenuation (db) figure 33. revision a figure 34. revision a1 figure 35. revision a2 using a1 values figure 36. revision a2 using a2* values
cs8427 ds477f1 59 20. revision history release date changes pp1 november 1999 1st preliminary release pp2 november 2000 2nd preliminary release pp3 may 2001 3rd preliminary release pp4 february 2003 4th preliminary release f1 january 2004 final release updated ?appendix c: pll filter? on page 54 to include information from errata er477e2 table 9. revision history contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warran ty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of li ability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for ge neral distribution, advertising or promotional purposes, or for creating any work for resale. an export permit needs to be obtained from the competent authorities of the japanese government if any of the products or techn ologies described in this material and controlled under the "foreign exchange and foreign trade law" is to be exported or taken out of japan. an export license an d/or quota needs to be obtained from the competent authorities of the chinese government if any of the products or technologies described in this material is s ubject to the prc foreign trade law and is to be exported or taken out of the prc. certain applications using semic onductor products may involve potential risks of death, personal in jury, or severe prop- erty or environmental damage (? critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military applications, products surgical ly implanted into the body, li fe support products or other critical applications (including medical devices, aircraft systems or components and personal or automotive safety or se- curity devices). inclusion of cirrus prod ucts in such applications is understood to be fully at the customer?s risk and cir- rus disclaims and makes no warranty, express, statutory or impl ied, including the implied warr anties of merchantability and fitness for particular purpose, wi th regard to any cirrus product that is used in such a manner. if the customer or cus- tomer?s customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to ful- ly indemnify cirrus, its officers, directors, employees, dist ributors and other agents from any and all liability, including attorneys? fees and costs, that may result fr om or arise in connec tion with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. i2c is a registered trademark of philips semiconductor. purchase of i2c components of cirrus logic, inc., or one of its sublice nsed associated companies conveys a license under the philips i2c patent rights to use those components in a standard i2c system.

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